From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 445A1384B11C; Wed, 24 Apr 2024 13:27:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 445A1384B11C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1713965278; bh=YIxQ9jrvgJKX8af4ec9EGrM3y5joat9oeBFN6JyqwtE=; h=From:To:Subject:Date:In-Reply-To:References:From; b=RKDZQkYMFZBruNpR90qT2vkK0E3f/iD1gahivBnsXRtEvBaRpkv7Wu3HLhyg3kdU0 F5DKOfy2vO1SH4MM4IS8kCmUtl+WqufSCei9HUeN6T6z+lADs3k+V7lTNPdt02asTu +jepsX6mnAwCPUw/Ak7yuBAKMAAdSvIzWS/QbMjI= From: "rsaxvc at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/53938] ARM target generates sub-optimal code (extra instructions) on load from memory Date: Wed, 24 Apr 2024 13:27:56 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 4.6.2 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: rsaxvc at gmail dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D53938 --- Comment #6 from rsaxvc at gmail dot com --- This also impacts Cortex-M0 & M23 on GCC13.2.0, just with the new extension instructions. Oddly, when loading a volatile u8 or u16 on Cortex-M3/4/7 does not generate extra zero extension instructions. But these cores do still have separate ldrb/ldrb + sxtab/sxtah sign extension instead of LDRSB/LDRSH.=