[Bug rtl-optimization/53942] New: unable to find a register to spill in class 'CREG'

[Bug rtl-optimization/53942] New: unable to find a register to spill in class 'CREG'

[ncahill_alt at yahoo dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53942

             Bug #: 53942
           Summary: unable to find a register to spill in class 'CREG'
    Classification: Unclassified
           Product: gcc
           Version: 4.7.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: ncahill_alt@yahoo.com


This command:

gcc -O2 -mtune=pentium2 -fno-inline -x c++ -std=gnu++98 -c a.c -o a.o

gives this output:

### output ###
a.c: In function 'unsigned char _ZL1fP2S_h.isra.0(UINT16, UINT16, UINT16,
unsigned char)':
a.c:25:1: error: unable to find a register to spill in class 'CREG'
a.c:25:1: error: this is the insn:
(insn 11 7 12 2 (parallel [
            (set (reg:SI 1 dx [85])
                (ashiftrt:SI (reg:SI 1 dx [85])
                    (reg/v:QI 81 [ i ])))
            (clobber (reg:CC 17 flags))
        ]) a.c:20 409 {*ashrsi3_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))
a.c:25: confused by earlier errors, bailing out
### end output ###

when compiling this testcase:

### a.c ###
typedef unsigned short UINT16;
typedef unsigned int UINT32;
typedef struct S_ S;

struct S_ {
  UINT16 data[3];
  UINT32 x;
  UINT32 y;
};

static inline S *get_S() {}

static unsigned char f(S *s, unsigned char i) 
{
  unsigned char c=0;
  unsigned char v;

  v = s->data[0]; 
  c|=v;
  v=((s->data[1])&(1<<i))?1:0; 
  c|=v<<1;
  v=((s->data[2])&0xff)&(1<<i); 
  c|=v<<2;
  return c;
}

void g() 
{
  S *s = get_S();
  s->x=f(s,6);
  s->y=f(s,7);
}
### end a.c ###

Using -mtune=i686 works.  I'm using gcc 4.7.1, i686-pc-linux-gnu, 32-bit.

Thank you.
Neil.

[Bug target/53942] [4.6/4.7/4.8 Regression] unable to find a register to spill in class 'CREG'

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53942

Uros Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |ra
             Target|                            |x86_32
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2012-07-13
            Summary|unable to find a register   |[4.6/4.7/4.8 Regression]
                   |to spill in class 'CREG'    |unable to find a register
                   |                            |to spill in class 'CREG'
     Ever Confirmed|0                           |1

--- Comment #1 from Uros Bizjak <ubizjak at gmail dot com> 2012-07-13 14:20:54 UTC ---
Confirmed, a regression at least on 4.6, 4.7 and 4.8.
Testcase compiles OK with 4.1.

RA issue.

[Bug rtl-optimization/53942] [4.6/4.7/4.8 Regression] unable to find a register to spill in class 'CREG'

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53942

Uros Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|ra                          |
          Component|target                      |rtl-optimization
   Target Milestone|---                         |4.6.4

--- Comment #2 from Uros Bizjak <ubizjak at gmail dot com> 2012-07-13 14:36:42 UTC ---
Please note that "static" function declaration enables register parameter
passing, so we have live AX, DX and CX at function entry.

combine pass propagates hard register to (insn 17):

(insn 17 16 18 2 (parallel [
            (set (reg:QI 90 [ D.1417 ])
                (and:QI (reg:QI 2 cx [ ISRA.5 ])
                    (subreg:QI (reg:SI 88 [ D.1419 ]) 0)))
            (clobber (reg:CC 17 flags))
        ]) pr53942.c:22 382 {*andqi_1}
     (expr_list:REG_DEAD (reg:HI 2 cx [ ISRA.5 ])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (expr_list:REG_DEAD (reg:SI 88 [ D.1419 ])
                (nil)))))

and this effectively blocks CX usage in between (insn 17) and function entry.
RA actually can't undo this propagation and fails to allocate CX when this is
the only alternative.

Reconfirmed as RTL optimization issue. Combine should not propagate hard
registers on its own.

[Bug rtl-optimization/53942] [4.6/4.7/4.8 Regression] unable to find a register to spill in class 'CREG'

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53942

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> 2012-07-16 11:31:59 UTC ---
C testcase for just -O2 -m32 -mtune=pentium2:
struct S
{
  unsigned short data[3];
  unsigned int x;
  unsigned int y;
};

struct S *baz (void);

__attribute__ ((noinline))
static unsigned char
foo (struct S *x, unsigned char y)
{
  unsigned char c = 0;
  unsigned char v = x->data[0];
  c |= v;
  v = ((x->data[1]) & (1 << y)) ? 1 : 0;
  c |= v << 1;
  v = ((x->data[2]) & 0xff) & (1 << y);
  c |= v << 2;
  return c;
}

void
bar (void)
{
  struct S *s = baz ();
  s->x = foo (s, 6);
  s->y = foo (s, 7);
}

cant_combine_insn_p already handles hard regs likely spilled correctly if they
are just seen in a simple register move, unfortunately in this case there is no
simple reg move, but instead a zero extension already in the *.expand dump:
(insn 4 3 5 2 (set (reg:SI 80 [ ISRA.4 ])
        (zero_extend:SI (reg:HI 2 cx [ ISRA.4 ]))) pr53942.c:12 -1
     (nil))
I wonder if either we shouldn't force the HI cx register first into pseudo and
have separate zero extension afterwards (the other alternative would be if we
have a zero or sign extension from hard register likely spilled, force the hard
register into a pseudo in the combiner at the spot where it used to be zero
extended).

[Bug rtl-optimization/53942] [4.6/4.7/4.8 Regression] unable to find a register to spill in class 'CREG'

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53942

--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> 2012-07-16 11:54:23 UTC ---
The following patch fixes this issue during expansion, don't have time right
now to test what effects it might have on generated code though:
--- gcc/function.c.jj    2012-06-25 08:38:26.000000000 +0200
+++ gcc/function.c    2012-07-16 13:41:52.847928315 +0200
@@ -2988,11 +2988,26 @@ assign_parm_setup_reg (struct assign_par
       && insn_operand_matches (icode, 1, op1))
     {
       enum rtx_code code = unsignedp ? ZERO_EXTEND : SIGN_EXTEND;
-      rtx insn, insns;
+      rtx insn, insns, t = op1;
       HARD_REG_SET hardregs;

       start_sequence ();
-      insn = gen_extend_insn (op0, op1, promoted_nominal_mode,
+      /* If op1 is a hard register that is likely spilled, first
+         force it into a pseudo, otherwise combiner might extend
+         its lifetime too much.  */
+      if (GET_CODE (t) == SUBREG)
+        t = SUBREG_REG (t);
+      if (REG_P (t)
+          && HARD_REGISTER_P (t)
+          && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (t))
+          && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (t))))
+        {
+          t = gen_reg_rtx (GET_MODE (op1));
+          emit_move_insn (t, op1);
+        }
+      else
+        t = op1;
+      insn = gen_extend_insn (op0, t, promoted_nominal_mode,
                   data->passed_mode, unsignedp);
       emit_insn (insn);
       insns = get_insns ();

[Bug rtl-optimization/53942] [4.6/4.7/4.8 Regression] unable to find a register to spill in class 'CREG'

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53942

--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> 2012-07-19 20:48:30 UTC ---
Author: jakub
Date: Thu Jul 19 20:48:25 2012
New Revision: 189681

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=189681
Log:
    PR rtl-optimization/53942
    * function.c (assign_parm_setup_reg): Avoid zero/sign extension
    directly from likely spilled non-fixed hard registers, move them
    to pseudo first.

    * gcc.dg/pr53942.c: New test.

Added:
    trunk/gcc/testsuite/gcc.dg/pr53942.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/function.c
    trunk/gcc/testsuite/ChangeLog

[Bug rtl-optimization/53942] [4.6/4.7/4.8 Regression] unable to find a register to spill in class 'CREG'

[izamyatin at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53942

Igor Zamyatin <izamyatin at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |izamyatin at gmail dot com

--- Comment #6 from Igor Zamyatin <izamyatin at gmail dot com> 2012-08-10 14:40:53 UTC ---
So trunk is ok. Any plans to backport changes to 4.7 and 4.6 and close this?

[Bug rtl-optimization/53942] [4.6/4.7/4.8 Regression] unable to find a register to spill in class 'CREG'

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53942

--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> 2012-08-13 07:35:11 UTC ---
Author: jakub
Date: Mon Aug 13 07:35:03 2012
New Revision: 190338

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=190338
Log:
    Backported from trunk
    2012-07-19  Jakub Jelinek  <jakub@redhat.com>

    PR rtl-optimization/53942
    * function.c (assign_parm_setup_reg): Avoid zero/sign extension
    directly from likely spilled non-fixed hard registers, move them
    to pseudo first.

    * gcc.dg/pr53942.c: New test.

Added:
    branches/gcc-4_7-branch/gcc/testsuite/gcc.dg/pr53942.c
Modified:
    branches/gcc-4_7-branch/gcc/ChangeLog
    branches/gcc-4_7-branch/gcc/function.c
    branches/gcc-4_7-branch/gcc/testsuite/ChangeLog

[Bug rtl-optimization/53942] [4.6 Regression] unable to find a register to spill in class 'CREG'

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53942

--- Comment #8 from Uros Bizjak <ubizjak at gmail dot com> 2012-09-02 13:57:01 UTC ---
The proposed patch from Comment #4 is not effective on 4.6 branch.

[Bug rtl-optimization/53942] [4.6 Regression] unable to find a register to spill in class 'CREG'

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53942

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|                            |FIXED
   Target Milestone|4.6.4                       |4.7.2

--- Comment #9 from Jakub Jelinek <jakub at gcc dot gnu.org> 2013-04-12 16:27:40 UTC ---
The 4.6 branch has been closed, fixed in GCC 4.7.2.