[Bug target/54300] New: [4.7/4.8 Regression] Erroneous optimization causes wrong Neon data management

["eric.batut at allegorithmic dot com" <gcc-bugzilla@gcc.gnu.org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54300

             Bug #: 54300
           Summary: [4.7/4.8 Regression] Erroneous optimization causes
                    wrong Neon data management
    Classification: Unclassified
           Product: gcc
           Version: 4.8.0
            Status: UNCONFIRMED
          Severity: major
          Priority: P3
         Component: target
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: eric.batut@allegorithmic.com


Created attachment 28044
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=28044
Small repro case

Using gcc trunk at rev 190381, compiled with the Android NDK r8b build-gcc.sh
script (so an arm-linux-androideabi target) and the command line below, the
attached repro case generates wrong code:

arm-linux-androideabi-g++ -march=armv7-a -mfloat-abi=softfp -mfpu=vfp
-mfpu=neon -marm -O2 test.cpp -S -o test.s

The core loop is pasted below:
    for(unsigned int sv=0 ; sv!=dv0 ; sv=(sv+s1v)&smask_v)
    {
        int32x4_t s;
        s = vmovl_s16(vget_low_s16(_loadlo_8i16((cv8i16*)_Inp, sv )));
        c = vaddq_s32(c, s);
    }

8 bytes are fetched from "_Inp (in bytes) + sv", then sign-extended from 4
16bits values to 4 32bits values, then accumulated in "c".

The generated assembly code for the loop is:
.L3:
    add    r4, r0, ip
    vmov.i32    d18, #0  @ v4hi   <= d18 is full of 0's
    add    ip, ip, r2
    vld1.16    {d19}, [r4:64]            <= d19 holds useful data
    and    ip, ip, r5
    cmp    r3, ip
    vswp    d18, d19                  <= d19 is now full of 0's
    vmovl.s16    q9, d19           <= d19 (full of 0's) gets expanded
    vadd.i32    q8, q8, q9        <= q9 is always zero when accumulated
    bne    .L3

When using "-O1" or "-O2 -fno-gcse", correct code is generated:
.L3:
    add    r4, r0, ip
    add    ip, ip, r2
    and    ip, ip, r5
    vld1.16    {d18}, [r4:64]            <= d18 holds useful data
    cmp    r3, ip
    vmovl.s16    q9, d18           <= d18 is sign-extended
    vadd.i32    q8, q8, q9        <= q9 is accumulated
    bne    .L3

This also happens with gcc 4.7.1, but not with gcc 4.6

Also, in the loadlo_8i16 function, if we replace the call to zero_64 by the
proper vdup_n_s16(0), then correct code is generated at -O2.

The (stripped down in the repro case) _v16u8_ and _v8u8_ structures are the way
we implemented some kind of compiler-performed polymorphism for Neon variables,
since not all ARM compilers have -flax-vector-conversions.