* [Bug target/54429] [SH] SImode values get ferried through FPUL and FP regs for -O0
2012-08-30 22:26 [Bug target/54429] New: [SH] SImode values get ferried through FPUL and FP regs for -O0 olegendo at gcc dot gnu.org
@ 2012-08-31 10:59 ` kkojima at gcc dot gnu.org
2012-08-31 11:54 ` olegendo at gcc dot gnu.org
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From: kkojima at gcc dot gnu.org @ 2012-08-31 10:59 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54429
--- Comment #1 from Kazumoto Kojima <kkojima at gcc dot gnu.org> 2012-08-31 10:59:44 UTC ---
(In reply to comment #0)
I don't know the history about it. I guess that the original
intention would be to use FP registers as fast memories for
integers, though I'm wrong about it. BTW, the last time I
tried to disable integer mode for FP registers, some reload
failures popped up in gcc testsuite. Are there no new failures
on your test with the above patch?
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/54429] [SH] SImode values get ferried through FPUL and FP regs for -O0
2012-08-30 22:26 [Bug target/54429] New: [SH] SImode values get ferried through FPUL and FP regs for -O0 olegendo at gcc dot gnu.org
2012-08-31 10:59 ` [Bug target/54429] " kkojima at gcc dot gnu.org
@ 2012-08-31 11:54 ` olegendo at gcc dot gnu.org
2012-11-13 8:45 ` olegendo at gcc dot gnu.org
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From: olegendo at gcc dot gnu.org @ 2012-08-31 11:54 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54429
--- Comment #2 from Oleg Endo <olegendo at gcc dot gnu.org> 2012-08-31 11:54:27 UTC ---
(In reply to comment #1)
> I don't know the history about it. I guess that the original
> intention would be to use FP registers as fast memories for
> integers, though I'm wrong about it. BTW, the last time I
> tried to disable integer mode for FP registers, some reload
> failures popped up in gcc testsuite. Are there no new failures
> on your test with the above patch?
I haven't done proper testing. I will check out what's happening there.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/54429] [SH] SImode values get ferried through FPUL and FP regs for -O0
2012-08-30 22:26 [Bug target/54429] New: [SH] SImode values get ferried through FPUL and FP regs for -O0 olegendo at gcc dot gnu.org
2012-08-31 10:59 ` [Bug target/54429] " kkojima at gcc dot gnu.org
2012-08-31 11:54 ` olegendo at gcc dot gnu.org
@ 2012-11-13 8:45 ` olegendo at gcc dot gnu.org
2012-11-13 22:25 ` olegendo at gcc dot gnu.org
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From: olegendo at gcc dot gnu.org @ 2012-11-13 8:45 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54429
--- Comment #3 from Oleg Endo <olegendo at gcc dot gnu.org> 2012-11-13 08:44:43 UTC ---
I've tested this:
Index: gcc/config/sh/sh.c
===================================================================
--- gcc/config/sh/sh.c (revision 193423)
+++ gcc/config/sh/sh.c (working copy)
@@ -12113,6 +12113,11 @@
if (FP_REGISTER_P (regno) && mode == SFmode)
return true;
+ if (FP_REGISTER_P (regno)
+ && !(GET_MODE_CLASS (mode) == MODE_FLOAT
+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT))
+ return false;
+
if (mode == V2SFmode)
{
if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
on rev 193423. There are a few failures on targets with HW FPU:
FAIL: gcc.c-torture/execute/20080502-1.c compilation
FAIL: gcc.c-torture/execute/ieee/copysign1.c compilation
FAIL: gcc.dg/builtins-32.c (internal compiler error)
FAIL: gcc.dg/builtins-50.c (internal compiler error)
FAIL: gcc.dg/pr48335-7.c (internal compiler error)
I'll check out the details.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/54429] [SH] SImode values get ferried through FPUL and FP regs for -O0
2012-08-30 22:26 [Bug target/54429] New: [SH] SImode values get ferried through FPUL and FP regs for -O0 olegendo at gcc dot gnu.org
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From: olegendo at gcc dot gnu.org @ 2012-11-13 22:25 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54429
--- Comment #4 from Oleg Endo <olegendo at gcc dot gnu.org> 2012-11-13 22:25:30 UTC ---
(In reply to comment #3)
> I've tested this:
>
> Index: gcc/config/sh/sh.c
> ===================================================================
> --- gcc/config/sh/sh.c (revision 193423)
> +++ gcc/config/sh/sh.c (working copy)
> @@ -12113,6 +12113,11 @@
> if (FP_REGISTER_P (regno) && mode == SFmode)
> return true;
>
> + if (FP_REGISTER_P (regno)
> + && !(GET_MODE_CLASS (mode) == MODE_FLOAT
> + || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT))
> + return false;
> +
> if (mode == V2SFmode)
> {
> if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
>
>
> on rev 193423. There are a few failures on targets with HW FPU:
>
It seems these problems happen on big endian targets only.
> FAIL: gcc.c-torture/execute/20080502-1.c compilation
Reload failure. Problematic insn:
(insn 12 44 13 2 (set (reg:SI 147 t)
(eq:SI (and:SI (reg:SI 1 r1 [166])
(subreg:SI (reg:DF 68 fr4 [ x ]) 0))
(const_int 0 [0]))) sh_tmp.cpp:110 1 {tstsi_t}
(expr_list:REG_DEAD (reg:SI 1 r1 [166])
(expr_list:REG_DEAD (reg:DF 68 fr4 [ x ])
(nil))))
> FAIL: gcc.c-torture/execute/ieee/copysign1.c compilation
Reload failure. Problematic insn:
(insn 10 41 11 2 (set (reg:SI 147 t)
(eq:SI (and:SI (reg:SI 1 r1 [165])
(subreg:SI (reg:DF 70 fr6 [ y ]) 0))
(const_int 0 [0]))) sh_tmp.cpp:67 1 {tstsi_t}
(expr_list:REG_DEAD (reg:SI 1 r1 [165])
(expr_list:REG_DEAD (reg:DF 70 fr6 [ y ])
(nil))))
> FAIL: gcc.dg/builtins-32.c (internal compiler error)
Reload failure. Problematic insn:
(insn 8 7 21 2 (set (reg:SI 0 r0 [164])
(and:SI (reg:SI 0 r0 [164])
(subreg:SI (reg:DF 68 fr4 [ x ]) 0))) sh_tmp.cpp:30 111
{*andsi_compact}
(expr_list:REG_DEAD (reg:DF 68 fr4 [ x ])
(nil)))
> FAIL: gcc.dg/builtins-50.c (internal compiler error)
Reload failure. Problematic insn:
(insn 10 43 11 2 (set (reg:SI 147 t)
(eq:SI (and:SI (reg:SI 1 r1 [165])
(subreg:SI (reg:DF 70 fr6 [ y ]) 0))
(const_int 0 [0]))) sh_tmp.cpp:24 1 {tstsi_t}
(expr_list:REG_DEAD (reg:SI 1 r1 [165])
(expr_list:REG_DEAD (reg:DF 70 fr6 [ y ])
(nil))))
> FAIL: gcc.dg/pr48335-7.c (internal compiler error)
Reload failure. Problematic insn:
(insn 9 3 10 2 (set (reg:SI 0 r0 [167])
(ashift:SI (subreg:SI (reg:DF 68 fr4 [ x ]) 0)
(const_int 8 [0x8]))) sh_tmp.cpp:28 149 {ashlsi3_k}
(expr_list:REG_DEAD (reg:DF 68 fr4 [ x ])
(nil)))
The problem is that 'arith_reg_operand' matches subregs of FP modes and so, for
example, combine folds insn sequences such as
(insn 8 7 9 2 (set (reg:SI 166)
(subreg:SI (reg:DI 165) 0)) sh_tmp.cpp:33 -1
(nil))
(insn 9 8 10 2 (set (reg:SI 167)
(ashift:SI (reg:SI 166)
(const_int 8 [0x8]))) sh_tmp.cpp:33 -1
(nil))
Adding this:
Index: gcc/config/sh/predicates.md
===================================================================
--- gcc/config/sh/predicates.md (revision 193423)
+++ gcc/config/sh/predicates.md (working copy)
@@ -156,7 +156,12 @@
if (REG_P (op))
regno = REGNO (op);
else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
- regno = REGNO (SUBREG_REG (op));
+ {
+ regno = REGNO (SUBREG_REG (op));
+ if (!(GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) == MODE_INT
+ || GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) ==
MODE_VECTOR_INT))
+ return false;
+ }
else
return 1;
makes the unwanted subreg propagation go away, but ends up in another reload
trouble:
sh_tmp.cpp:92:1: error: unable to find a register to spill in class
'TARGET_REGS'
}
^
sh_tmp.cpp:92:1: error: this is the insn:
(insn 7 4 8 2 (set (reg:SI 1 r1 [165])
(subreg:SI (reg:DF 70 fr6 [ y ]) 0)) sh_tmp.cpp:91 244 {movsi_ie}
(expr_list:REG_DEAD (reg:DF 70 fr6 [ y ])
(nil)))
On little endian this problem does not happen and the same insn right before
the reload pass looks like:
(insn 7 4 8 2 (set (reg:SI 165)
(subreg:SI (reg/v:DF 163 [ y ]) 4)) sh_tmp.cpp:91 244 {movsi_ie}
(expr_list:REG_DEAD (reg/v:DF 163 [ y ])
(nil)))
Notice that on big endian the insn contains hard regs.
I've tried tapping sh_secondary_reload and there are some weird things
happening such as:
in = 1 rlcass = 8 mode = SI x = (reg:DF 70 fr6 [ y ])
--> rclass = 5
This is caused by the way sh_cannot_change_mode_class handles stuff on big
endian. Adding this to 'sh_cannot_change_mode_class':
if (from == DFmode && to == SImode)
return true;
fixes at least one of the test cases, but I'm totally unaware of the
consequences.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/54429] [SH] SImode values get ferried through FPUL and FP regs for -O0
2012-08-30 22:26 [Bug target/54429] New: [SH] SImode values get ferried through FPUL and FP regs for -O0 olegendo at gcc dot gnu.org
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From: olegendo at gcc dot gnu.org @ 2012-11-14 9:45 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54429
--- Comment #5 from Oleg Endo <olegendo at gcc dot gnu.org> 2012-11-14 09:45:22 UTC ---
(In reply to comment #4)
>
> makes the unwanted subreg propagation go away, but ends up in another reload
> trouble:
>
> sh_tmp.cpp:92:1: error: unable to find a register to spill in class
> 'TARGET_REGS'
> }
> ^
> sh_tmp.cpp:92:1: error: this is the insn:
> (insn 7 4 8 2 (set (reg:SI 1 r1 [165])
> (subreg:SI (reg:DF 70 fr6 [ y ]) 0)) sh_tmp.cpp:91 244 {movsi_ie}
> (expr_list:REG_DEAD (reg:DF 70 fr6 [ y ])
> (nil)))
>
The test case I was using for tracking this:
extern double copysign(double,double);
double test1(double x, double y)
{
return copysign(-x,y);
}
Interestingly, without any patches applied, compiling the function above with
-O2 -m4 -ml results in:
_test1:
fmov.s fr6,@-r15 ! 49 movsf_ie/7 [length = 2]
fmov.s fr7,@-r15 ! 50 movsf_ie/7 [length = 2]
mov.l .L8,r1 ! 43 movsi_ie/1 [length = 2]
mov.l @r15+,r2 ! 51 movdf_k/3 [length = 4]
mov.l @r15+,r3
tst r3,r1 ! 10 tstsi_t/2 [length = 2]
fmov fr4,fr0 ! 52 movsf_ie/1 [length = 2]
fmov fr5,fr1 ! 53 movsf_ie/1 [length = 2]
bt/s .L6 ! 11 *cbranch_t [length = 2]
fabs dr0 ! 9 absdf2_i [length = 2]
fneg dr0 ! 12 negdf2_i [length = 2]
.L6:
rts
nop ! 56 *return_i [length = 4]
.L9:
.align 2
.L8:
.long -2147483648
and -O2 -m4 -mb is:
_test1:
flds fr6,fpul ! 46 movsi_ie/22 [length = 2]
sts fpul,r1 ! 47 movsi_ie/20 [length = 2]
fmov fr4,fr0 ! 48 movsf_ie/1 [length = 2]
fmov fr5,fr1 ! 49 movsf_ie/1 [length = 2]
cmp/pz r1 ! 10 cmpgesi_t/1 [length = 2]
bt/s .L6 ! 11 *cbranch_t [length = 2]
fabs dr0 ! 9 absdf2_i [length = 2]
fneg dr0 ! 12 negdf2_i [length = 2]
.L6:
rts
nop ! 52 *return_i [length = 4]
This is probably due to the 'sh_cannot_change_mode_class'. On big endian the
DFmode reg can be accessed as SImode, but not on little endian because of the
subreg ordering. Maybe it would be better to not do all the GP <-> FPUL <-> FP
reg transfers during reload but emit the necessary insn sequences before
reload.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/54429] [SH] SImode values get ferried through FPUL and FP regs for -O0
2012-08-30 22:26 [Bug target/54429] New: [SH] SImode values get ferried through FPUL and FP regs for -O0 olegendo at gcc dot gnu.org
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2014-12-27 11:41 ` olegendo at gcc dot gnu.org
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From: olegendo at gcc dot gnu.org @ 2014-10-12 17:28 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54429
--- Comment #6 from Oleg Endo <olegendo at gcc dot gnu.org> ---
A test case for this problem is gcc/testsuite/g++.dg/tls/thread_local-order1.C,
which is compiled without optimizations and contains the following sequence:
stc gbr,r1
mov.l .L20,r2
add r2,r1
lds r1,fpul
fsts fpul,fr1
flds fr1,fpul
sts fpul,r0
mov r14,r15
lds.l @r15+,pr
mov.l @r15+,r14
rts
nop
what the code is actually doing:
stc gbr,r1
mov.l .L20,r2
add r2,r1
mov r1,r0
mov r14,r15
lds.l @r15+,pr
mov.l @r15+,r14
rts
nop
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/54429] [SH] SImode values get ferried through FPUL and FP regs for -O0
2012-08-30 22:26 [Bug target/54429] New: [SH] SImode values get ferried through FPUL and FP regs for -O0 olegendo at gcc dot gnu.org
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From: olegendo at gcc dot gnu.org @ 2014-12-27 11:41 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54429
--- Comment #7 from Oleg Endo <olegendo at gcc dot gnu.org> ---
Another minimal test case:
int var;
int test (void)
{
return var;
}
mov.l r14,@-r15
mov r15,r14
mov.l .L3,r1
mov.l @r1,r1
lds r1,fpul
fsts fpul,fr1
flds fr1,fpul
sts fpul,r0
mov r14,r15
mov.l @r15+,r14
rts
nop
.L4:
.align 2
.L3:
.long _var
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/54429] [SH] SImode values get ferried through FPUL and FP regs for -O0
2012-08-30 22:26 [Bug target/54429] New: [SH] SImode values get ferried through FPUL and FP regs for -O0 olegendo at gcc dot gnu.org
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From: olegendo at gcc dot gnu.org @ 2014-12-27 13:56 UTC (permalink / raw)
To: gcc-bugs
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--- Comment #8 from Oleg Endo <olegendo at gcc dot gnu.org> ---
BTW, the problem is also there when using LRA.
^ permalink raw reply [flat|nested] 9+ messages in thread