From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13434 invoked by alias); 11 Oct 2012 13:48:48 -0000 Received: (qmail 12620 invoked by uid 48); 11 Oct 2012 13:48:06 -0000 From: "olegendo at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/54602] [SH] Register pop insn not put in rts delay slot Date: Thu, 11 Oct 2012 13:48:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Keywords: X-Bugzilla-Severity: enhancement X-Bugzilla-Who: olegendo at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2012-10/txt/msg01078.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54602 --- Comment #6 from Oleg Endo 2012-10-11 13:48:04 UTC --- (In reply to comment #5) > (In reply to comment #4) > > > > I don't know the history about it. I can only imagine that some > > system could assume some banked regs will be not clobbered with > > their exception handler and will be used like as normal registers. > > A new -m option which controls the behavior of which default > > is not to save/restore the banked regs? > > Oh well, why not ;) > But first I'd like to think this through. I'll open a new PR for it later. Turns out, there's already something there: 'nosave_low_regs' function attribute, which is documented only in the source code: sh.c (line ~9300): nosave_low_regs - don't save r0..r7 in an interrupt handler. This is useful on the SH3 and upwards, which has a separate set of low regs for User and Supervisor modes. This should only be used for the lowest level of interrupts. Higher levels of interrupts must save the registers in case they themselves are interrupted. I will improve the documentation regarding this.