[Bug target/54682] New: [SH] Replace constant loads with reg-reg copies

[Bug target/54682] New: [SH] Replace constant loads with reg-reg copies

[olegendo at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54682

             Bug #: 54682
           Summary: [SH] Replace constant loads with reg-reg copies
    Classification: Unclassified
           Product: gcc
           Version: 4.8.0
            Status: UNCONFIRMED
          Severity: enhancement
          Priority: P3
         Component: target
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: olegendo@gcc.gnu.org
            Target: sh*-*-*


I've noticed that quite often code such as this is generated:

  mov   #15,r4
  mov   r0,r8
  mov   #0,r5
  mov   #0,r6
  jsr   @r10
  mov   #0,r7

On SH4A the insn 'mov #imm,Rn' is a MT group insn and can be executed in
parallel. On SH4 this is an EX group insn and can't be executed in parallel.
Moreover on SH4 and SH2A the insn 'mov Rm,Rn' is a zero-latency insn and can be
executed in parallel with any other insn.  Thus the above sequence should be
something like:

  mov   #15,r4
  mov   r0,r8
  mov   #0,r5
  mov   r5,r6
  jsr   @r10
  mov   r5,r7

As far as I know these constant loads might also be generated during reload. 
Peepholes probably won't catch all opportunities, since constant loads can be
disjunct.  Probably this could be done by split patterns after reload, which
look for preceding constant loads and split into reg-reg moves.

[Bug target/54682] [SH] Replace constant loads with reg-reg copies

[olegendo at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54682

--- Comment #1 from Oleg Endo <olegendo at gcc dot gnu.org> 2012-10-10 22:17:13 UTC ---
Another thing that could be considered are T bit stores via the 'movt' insn. 
For example:
   movt   r2       ! EX
   < something else; r2, T not modified>
   movt   r4       ! EX

can be turned into

   movt   r2       ! EX
   < something else; r2, T not modified>
   mov    r2,r4    ! MT

[Bug target/54682] [SH] Replace constant loads with reg-reg copies

[olegendo at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54682

--- Comment #2 from Oleg Endo <olegendo at gcc dot gnu.org> ---
A related case, but the other way around:

#include <bitset>

std::bitset<32> make_bits (void)
{
  std::bitset<32> r;
  for (auto&& i : { 4, 5, 6, 10 })
    if (i < r.size ())
      r.set (i);

  return r;
}

results in the following code (-O2):

        mov.l   .L8,r1
        mov     #0,r0
        mov     #31,r7
        mov     #1,r6   // load constant '1' for '1 << x'
        mov     #4,r2
.L2:
        mov.l   @r1,r3
        cmp/hi  r7,r3
        bf/s    .L7
        mov     r6,r5   // copy constant '1' to r5
.L3:
        dt      r2
        bf/s    .L2
        add     #4,r1
        rts
        nop
        .align 1
.L7:
        shld    r3,r5  // r5 <<= r3
        bra     .L3
        or      r5,r0

In this case one register is used to hold an imm8 constant that can be loaded
with a single insn.  Even though the insn 'mov Rm,Rn' is a zero-latency on SH4
and SH2A, freeing one register might result in better overall code.

[Bug target/54682] [SH] Replace constant loads with reg-reg copies

[olegendo at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54682

--- Comment #3 from Oleg Endo <olegendo at gcc dot gnu.org> ---
A related case from CSiBE, linux-2.4.23-pre3-testplatform/net/ipv4/igmp.c,
function _add_grhead:

.L275:
        mov     #0,r0
        mov.b   r11,@r8
        mov.b   r0,@(1,r8)
        mov     #0,r0        << redundant constant load
        mov.w   r0,@(2,r8)
        mov.l   @(4,r10),r1
        mov.l   r1,@(4,r8)
        mov.l   @(32,r9),r1
        mov.w   @(6,r1),r0

The redundant load of 'r0' with constant '0' is probably introduced by reload. 
If converted to 'mov r0,r0' it would probably be eliminated automatically.