[Bug tree-optimization/54742] Switch elimination in FSM loop

["joey.ye at arm dot com" <gcc-bugzilla@gcc.gnu.org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54742

--- Comment #35 from Joey Ye <joey.ye at arm dot com> ---
Here is good expansion:
;; _41 = _42 * 4;

(insn 20 19 0 (set (reg:SI 126 [ D.5038 ])
        (ashift:SI (reg/v:SI 131 [ Int_1_Par_Val ])
            (const_int 2 [0x2]))) -1
     (nil))

;; _40 = _2 + _41;

(insn 21 20 22 (set (reg:SI 136 [ D.5035 ])
        (plus:SI (reg/v/f:SI 130 [ Arr_2_Par_Ref ])
            (reg:SI 119 [ D.5036 ]))) -1
     (nil))

(insn 22 21 0 (set (reg/f:SI 125 [ D.5035 ])
        (plus:SI (reg:SI 136 [ D.5035 ])
            (reg:SI 126 [ D.5038 ]))) -1
     (nil))


;; MEM[(int[25] *)_51 + 20B] = _34;

(insn 29 28 30 (set (reg:SI 139)
        (plus:SI (reg/v/f:SI 130 [ Arr_2_Par_Ref ])
            (reg:SI 119 [ D.5036 ]))) Proc_8.c:23 -1
     (nil))

(insn 30 29 31 (set (reg:SI 140)
        (plus:SI (reg:SI 139)
            (reg:SI 126 [ D.5038 ]))) Proc_8.c:23 -1
     (nil))

(insn 31 30 32 (set (reg/f:SI 141)
        (plus:SI (reg:SI 140)
            (const_int 1000 [0x3e8]))) Proc_8.c:23 -1
     (nil))

(insn 32 31 0 (set (mem:SI (plus:SI (reg/f:SI 141)
                (const_int 20 [0x14])) [2 MEM[(int[25] *)_51 + 20B]+0 S4 A32])
        (reg:SI 124 [ D.5039 ])) Proc_8.c:23 -1
     (nil))

After cse1 140 can be replaced by 125, thus lead a series of transformation
make it much more efficient.

Here is bad expansion:
;; _40 = Arr_2_Par_Ref_22(D) + _12;

(insn 22 21 23 (set (reg:SI 138 [ D.5038 ])
        (plus:SI (reg:SI 128 [ D.5038 ])
            (reg:SI 121 [ D.5036 ]))) -1
     (nil))

(insn 23 22 0 (set (reg/f:SI 127 [ D.5035 ])
        (plus:SI (reg/v/f:SI 132 [ Arr_2_Par_Ref ])
            (reg:SI 138 [ D.5038 ]))) -1
     (nil))

;; _32 = _20 + 1000;

(insn 29 28 0 (set (reg:SI 124 [ D.5038 ])
        (plus:SI (reg:SI 121 [ D.5036 ])
            (const_int 1000 [0x3e8]))) Proc_8.c:23 -1
     (nil))

;; MEM[(int[25] *)_51 + 20B] = _34;

(insn 32 31 33 (set (reg:SI 141)
        (plus:SI (reg/v/f:SI 132 [ Arr_2_Par_Ref ])
            (reg:SI 124 [ D.5038 ]))) Proc_8.c:23 -1
     (nil))

(insn 33 32 34 (set (reg/f:SI 142)
        (plus:SI (reg:SI 141)
            (reg:SI 128 [ D.5038 ]))) Proc_8.c:23 -1
     (nil))

(insn 34 33 0 (set (mem:SI (plus:SI (reg/f:SI 142)
                (const_int 20 [0x14])) [2 MEM[(int[25] *)_51 + 20B]+0 S4 A32])
        (reg:SI 126 [ D.5039 ])) Proc_8.c:23 -1
     (nil))

Here cse doesn't happen, resulting in less optimal insns. Reason why cse
doesn't happen is unclear yet.