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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/55583] Extended shift instruction on x86-64 is not used,
 producing unoptimal code
Date: Tue, 01 Nov 2022 03:24:05 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D55583

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:5c5ef2f9ab545b680cd4bb6c540a9dadb12ead86

commit r13-3586-g5c5ef2f9ab545b680cd4bb6c540a9dadb12ead86
Author: liuhongt <hongtao.liu@intel.com>
Date:   Thu Oct 27 18:48:41 2022 +0800

    Enable more optimization for 32-bit/64-bit shrd/shld with imm shift cou=
nt.

    This patch doens't handle variable count since it require 5 insns to
    be combined to get wanted pattern, but current pass_combine only
    supports at most 4.
    This patch doesn't handle 16-bit shrd/shld either.

    gcc/ChangeLog:

            PR target/55583
            * config/i386/i386.md (*x86_64_shld_1): Rename to ..
            (x86_64_shld_1): .. this.
            (*x86_shld_1): Rename to ..
            (x86_shld_1): .. this.
            (*x86_64_shrd_1): Rename to ..
            (x86_64_shrd_1): .. this.
            (*x86_shrd_1): Rename to ..
            (x86_shrd_1): .. this.
            (*x86_64_shld_shrd_1_nozext): New pre_reload splitter.
            (*x86_shld_shrd_1_nozext): Ditto.
            (*x86_64_shrd_shld_1_nozext): Ditto.
            (*x86_shrd_shld_1_nozext): Ditto.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr55583.c: New test.=