From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4572 invoked by alias); 2 Mar 2013 15:23:31 -0000 Received: (qmail 4530 invoked by uid 48); 2 Mar 2013 15:23:13 -0000 From: "web at brolinembedded dot se" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/55757] Suboptimal interrupt prologue/epilogue for ARMv7-M (Cortex-M3) Date: Sat, 02 Mar 2013 15:23:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: web at brolinembedded dot se X-Bugzilla-Status: NEW X-Bugzilla-Priority: P5 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: CC Message-ID: In-Reply-To: References: X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2013-03/txt/msg00122.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55757 Timmy Brolin changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |web at brolinembedded dot | |se --- Comment #7 from Timmy Brolin 2013-03-02 15:23:11 UTC --- (In reply to comment #2) > If you really know that you don't need stack-alignment on an M3, then just > remove the interrupt attribute. It really doesn't serve any other purpose on > M-profile cores other than to cause the stack realignment. What you suggest requires a change in the C-code depending on the processor. That is, one piece of C-code will not compile optimally for different Cortex-M3 revisions without modifications to the C-code itself. This is not good for code which is intended to be used on multiple platforms. Cortex-M3 r0p0 needs the prologue/epilogue. Cortex-M3 r1p0 has a new configuration bit called STKALIGN which when enabled makes the prologue/epilogue unnecessary. (But the default setting is that it still needs the prologue/epilogue) Cortex-M3 r2p0 changed the default setting of STKALIGN so that the prologue/epilogue are unnecessary by default. I would suggest that the prologue/epilogue should be removed by default when compiling for r2p0 or higher, but be kept by default for older revisions. There should also be a compilation switch to manually enable/disable the prologue/epilogue according to the chosen setting of STKALIGN. Interrupts can often be time critical, so ISR entry is probably the worst possible place for extra instructions.