[Bug rtl-optimization/57189] New: [4.9 Regression] Vector register is spilled for vector extract pattern

[Bug rtl-optimization/57189] New: [4.9 Regression] Vector register is spilled for vector extract pattern

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

             Bug #: 57189
           Summary: [4.9 Regression] Vector register is spilled for vector
                    extract pattern
    Classification: Unclassified
           Product: gcc
           Version: 4.9.0
            Status: UNCONFIRMED
          Keywords: ra
          Severity: normal
          Priority: P3
         Component: rtl-optimization
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: ubizjak@gmail.com
            Target: x86


Following testcase:

--cut here--
typedef int __v4si __attribute__ ((__vector_size__ (16)));

int test (__v4si __A)
{
  return __builtin_ia32_vec_ext_v4si (__A, 0);
}
--cut here--

compiled with '-O2 -msse2 -march=k8" generates:

test:
        movaps  %xmm0, -24(%rsp)
        movl    -24(%rsp), %eax
        ret

where 4.8 generates:

test:
        movd    %xmm0, -12(%rsp)
        movl    -12(%rsp), %eax
        ret

The problem is with IRA, which spills V4SImode, where reload spills SImode
register for:

(insn 6 3 12 2 (set (reg:SI 62)
        (vec_select:SI (reg/v:V4SI 61 [ __A ])
            (parallel [
                    (const_int 0 [0])
                ]))) t.c:5 1618 {*vec_extractv4si_0}


 This memory mismatch could lead to a partial memory stall.

[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

[rguenth at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |4.9.0

[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

[rguenth at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |missed-optimization
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2013-05-07
     Ever Confirmed|0                           |1

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> 2013-05-07 08:51:45 UTC ---
In particular store forwarding will likely not work

[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

[graham.stott at btinternet dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

--- Comment #2 from graham.stott at btinternet dot com ---
________________________________
 From: rguenth at gcc dot gnu.org <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org 
Sent: Friday, 25 October 2013, 14:11
Subject: [Bug rtl-optimization/57189] [4.9 Regression] Vector register is
spilled for vector extract pattern


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|P3                          |P1
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Subject: [Bug rtl-optimization/56738] [4.9 Regression] ICE in c-c++-common/torture/vshuf-v4di.c
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http://gcc.gnu.org/bugzilla/show_bug.cgi?idV738

--- Comment #6 from ktkachov at gcc dot gnu.org ---
(In reply to Richard Biener from comment #5)
> Is this fixed now?

Fixed on arm. Nature of the fix seems to suggest that powerpc should be fixed
as well?

[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Likely caused by r198611.

[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

--- Comment #4 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Jakub Jelinek from comment #3)
> Likely caused by r198611.

This is the patch that exposes the problem.

I have filled this PR due to the difference with IRA vs. reload, it looks that
spill size should be somehow taken into account.
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Subject: [Bug sanitizer/59136] [4.9 Regression] llvm-symbolizer shouldn't be started always
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http://gcc.gnu.org/bugzilla/show_bug.cgi?idY136

--- Comment #10 from Alexey Samsonov <samsonov at google dot com> ---
Hi!

Jakub suggested to use libbacktrace in libsanitizer. I've committed his patch
to LLVM, and it will soon be merged into GCC, with many more changes. So, your
change will not be needed. I've also ensured that, if you use llvm-symbolizer,
it will not be started always, only when we actually need it to print a
symbolized stack trace.

Regarding "llvm-symbolizer: Unknown command line argument
'--default-arch=x86_64'" failure: you see this because you don't use the trunk
version of llvm-symbolizer binary. Sorry about that - we can keep ASan runtime
in sync with LLVM head, but we surely get such dependency problems when we move
it anywhere.

[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #4)
> (In reply to Jakub Jelinek from comment #3)
> > Likely caused by r198611.
> 
> This is the patch that exposes the problem.
> 
> I have filled this PR due to the difference with IRA vs. reload, it looks
> that spill size should be somehow taken into account.

What was the point of the r198611 patch other than macroizing some insns
though?
Isn't it worth to just restore the previous behavior when it worked properly
with both reload and LRA?
>From gcc-bugs-return-437825-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Tue Dec 17 11:12:48 2013
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Subject: [Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA
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http://gcc.gnu.org/bugzilla/show_bug.cgi?idY535

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[4.9 regression] -Os code   |[4.9 regression] -Os code
                   |size regressions for        |size regressions for
                   |Thumb1/Thumb2 (with LRA)?   |Thumb1/Thumb2 with LRA

--- Comment #3 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
It seems that one of the major problems is a significant increase in the number
of mov instructions to copy registers from one location to another.  This is
probably due to the two-operand format instructions we have in Thumb.

[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Jakub Jelinek from comment #5)
> (In reply to Uroš Bizjak from comment #4)
> > (In reply to Jakub Jelinek from comment #3)
> > > Likely caused by r198611.
> > 
> > This is the patch that exposes the problem.
> > 
> > I have filled this PR due to the difference with IRA vs. reload, it looks
> > that spill size should be somehow taken into account.
> 
> What was the point of the r198611 patch other than macroizing some insns
> though?
> Isn't it worth to just restore the previous behavior when it worked properly
> with both reload and LRA?

The patch added missing alternative (xmm->mem, IIRC) that exposed this problem.
Since there is no other weight in play, IRA is now free to spill V4SI input
value from xmm register and later parially load SImode to an integer register.
However, we have better alternative at hand, where we can spill SImode value.

Many other examples can be constructed for -march=k8, where interunit moves are
disabled. -march=core2 and other intel processors are immune to this problem.

This is the reason why I think this problem should be solved in IRA in a
generic way. IRA should choose the most appropriate register spill out of
otherwise equal choices based on some criteria, so we won't have to
artificially limit insn alternatives.
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Subject: [Bug ipa/59265] [4.9 Regression] Segmentation fault in ipa_note_param_call for -fprofile-use in SPEC CPU2006
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http://gcc.gnu.org/bugzilla/show_bug.cgi?idY265

--- Comment #21 from Markus Trippelsdorf <trippels at gcc dot gnu.org> ---
(In reply to Jan Hubicka from comment #20)
> Hmm, it may be someone altering the insns during streaming process.  You may
> try to check
> who is doing that while streaming out the relevant .o file.
> Is it compilation->linker streaming or wpa->ltrans?

It is wpa->ltrans:
 *** [/tmp/ccgCD7yp.ltrans19.ltrans.o] Error 1

> UIDs are initialized in renumber_gimple_stmt_uids calls in passes.c and then
> you can
> try to check if someone touch the statements....
>
> I will try to check if I spot something obvoius, but probably only tomorrow.

I've tried to bisect the issue, but it's messy.
However I think I can rule out any commit since r205447.
If r205447 is the culprit I cannot say for sure,
because Firefox ICEs during the build.

[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

[vmakarov at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

--- Comment #8 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
Author: vmakarov
Date: Thu Mar 13 15:52:50 2014
New Revision: 208549

URL: http://gcc.gnu.org/viewcvs?rev=208549&root=gcc&view=rev
Log:
2014-03-13  Vladimir Makarov  <vmakarov@redhat.com>

    PR rtl-optimization/57189
    * lra-constraints.c (process_alt_operands): Disfavor spilling
    vector pseudos.

2014-03-13  Vladimir Makarov  <vmakarov@redhat.com>

    PR rtl-optimization/57189
    * gcc.target/i386/pr57189.c: New.

Added:
    trunk/gcc/testsuite/gcc.target/i386/pr57189.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/lra-constraints.c
    trunk/gcc/testsuite/ChangeLog

[Bug rtl-optimization/57189] [4.9 Regression] Vector register is spilled for vector extract pattern

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #9 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Thanks, Vladimir.