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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/57189] New: [4.9 Regression] Vector register is spilled for vector extract pattern Date: Mon, 06 May 2013 17:46:00 -0000 [thread overview] Message-ID: <bug-57189-4@http.gcc.gnu.org/bugzilla/> (raw) http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189 Bug #: 57189 Summary: [4.9 Regression] Vector register is spilled for vector extract pattern Classification: Unclassified Product: gcc Version: 4.9.0 Status: UNCONFIRMED Keywords: ra Severity: normal Priority: P3 Component: rtl-optimization AssignedTo: unassigned@gcc.gnu.org ReportedBy: ubizjak@gmail.com Target: x86 Following testcase: --cut here-- typedef int __v4si __attribute__ ((__vector_size__ (16))); int test (__v4si __A) { return __builtin_ia32_vec_ext_v4si (__A, 0); } --cut here-- compiled with '-O2 -msse2 -march=k8" generates: test: movaps %xmm0, -24(%rsp) movl -24(%rsp), %eax ret where 4.8 generates: test: movd %xmm0, -12(%rsp) movl -12(%rsp), %eax ret The problem is with IRA, which spills V4SImode, where reload spills SImode register for: (insn 6 3 12 2 (set (reg:SI 62) (vec_select:SI (reg/v:V4SI 61 [ __A ]) (parallel [ (const_int 0 [0]) ]))) t.c:5 1618 {*vec_extractv4si_0} This memory mismatch could lead to a partial memory stall.
next reply other threads:[~2013-05-06 17:46 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-05-06 17:46 ubizjak at gmail dot com [this message] 2013-05-07 8:51 ` [Bug rtl-optimization/57189] " rguenth at gcc dot gnu.org 2013-05-07 8:51 ` rguenth at gcc dot gnu.org 2013-10-25 13:13 ` graham.stott at btinternet dot com 2013-11-27 11:48 ` jakub at gcc dot gnu.org 2013-11-27 11:55 ` ubizjak at gmail dot com 2013-12-17 11:12 ` jakub at gcc dot gnu.org 2013-12-17 11:33 ` ubizjak at gmail dot com 2014-03-13 15:53 ` vmakarov at gcc dot gnu.org 2014-03-13 15:56 ` jakub at gcc dot gnu.org
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