From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 45192 invoked by alias); 5 May 2015 09:46:32 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 45107 invoked by uid 48); 5 May 2015 09:46:25 -0000 From: "chefmax at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug c++/57271] ARM: gcc generates insufficient alignment for memory passed as extra argument for function return large composite type Date: Tue, 05 May 2015 09:46:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: c++ X-Bugzilla-Version: 4.8.1 X-Bugzilla-Keywords: X-Bugzilla-Severity: major X-Bugzilla-Who: chefmax at gcc dot gnu.org X-Bugzilla-Status: WAITING X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cf_gcctarget cc cf_gcchost cf_known_to_fail Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-05/txt/msg00330.txt.bz2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57271 Maxim Ostapenko changed: What |Removed |Added ---------------------------------------------------------------------------- Target|arm |arm-linux-gnueabi CC| |chefmax at gcc dot gnu.org, | |ygribov at gcc dot gnu.org Host| |x86_64-pc-linux-gnu Known to fail| |6.0 --- Comment #7 from Maxim Ostapenko --- I've ran to the exactly the same issue on armv7-a (cortex-A8) target with trunk compiler and pr55073.C testcase: $ ~/install/gcc-trunk-arm/armv7l-tizen/bin/armv7l-tizen-linux-gnueabi-gcc ~/workspace/downloads/gcc/gcc/testsuite/gcc.target/arm/pr55073.C -O2 -mcpu=cortex-a8 -lm -o ./pr55073.exe $ ~/install/gcc-5.0-arm/armv7l-tizen/bin/armv7l-tizen-linux-gnueabi-gcc -v Using built-in specs. COLLECT_GCC=/home/max/install/gcc-trunk-arm/armv7l-tizen/bin/armv7l-tizen-linux-gnueabi-gcc COLLECT_LTO_WRAPPER=/home/max/install/gcc-trunk-arm/armv7l-tizen/libexec/gcc/armv7l-tizen-linux-gnueabi/6.0.0/lto-wrapper Target: armv7l-tizen-linux-gnueabi Configured with: /home/max/build/v6/sources/gcc_1/configure --build=x86_64-pc-linux-gnu --host=x86_64-pc-linux-gnu --target=armv7l-tizen-linux-gnueabi --prefix=/home/max/install/gcc-trunk-arm/armv7l-tizen --with-sysroot=/home/max/install/gcc-trunk-arm/armv7l-tizen/armv7l-tizen-linux-gnueabi/sys-root --disable-libmudflap --enable-libssp --disable-nls --disable-libstdcxx-pch --disable-multilib --disable-gnu-unique-object --enable-linker-build-id --with-mode=arm --with-fpu=neon-vfpv4 --with-arch=armv7-a --with-tune=cortex-a15.cortex-a7 --with-float=softfp --enable-libgomp --enable-poison-system-directories --enable-long-long --enable-threads --enable-languages=c,c++,fortran --enable-shared --enable-lto --enable-symvers=gnu --enable-__cxa_atexit --with-gnu-as --with-gnu-ld --with-host-libstdcxx='-static-libgcc -Wl,-Bstatic,-lstdc++,-Bdynamic -lm' -- Thread model: posix gcc version 6.0.0 20150505 (experimental) Looking to gdb output: Breakpoint 1, 0x00008608 in test_func() () (gdb) disas Dump of assembler code for function _Z9test_funcv: 0x000085b4 <+0>: movw r3, #34480 ; 0x86b0 0x000085b8 <+4>: movt r3, #0 0x000085bc <+8>: add r2, r3, #16 0x000085c0 <+12>: vld1.8 {d20-d21}, [r3 :128] 0x000085c4 <+16>: vld1.8 {d16-d17}, [r2 :128] 0x000085c8 <+20>: vorr d17, d20, d20 0x000085cc <+24>: vorr d18, d16, d16 0x000085d0 <+28>: vzip.8 d16, d20 0x000085d4 <+32>: vzip.8 d17, d18 0x000085d8 <+36>: vorr d20, d16, d16 0x000085dc <+40>: vorr d18, d17, d17 0x000085e0 <+44>: vorr d22, d16, d16 0x000085e4 <+48>: vzip.8 d20, d18 0x000085e8 <+52>: vzip.8 d17, d22 0x000085ec <+56>: vorr d18, d20, d20 0x000085f0 <+60>: vmov.i16 q12, #2 ; 0x0002 0x000085f4 <+64>: vmovl.s8 q10, d17 0x000085f8 <+68>: vmovl.s8 q9, d18 0x000085fc <+72>: vsub.i16 q10, q10, q12 0x00008600 <+76>: vsub.i16 q8, q9, q12 0x00008604 <+80>: vadd.i16 q8, q10, q8 => 0x00008608 <+84>: vst1.64 {d16-d17}, [r0 :128] 0x0000860c <+88>: bx lr End of assembler dump. r0 0xbe3ffc58 3191864408 (gdb) vst1.64 wants r0 to be 128-bit aligned, but it's only 64-bit aligned here. Documentation from ARM info center (http://infocenter.arm.com/help/index.jsp? topic=/com.arm.doc.ddi0344c/Cihejdic.html) points here for cortex-a8: "If an alignment qualifier is specified, a check is made for strict alignment based on the qualifier, independent of the A-bit setting." So, bus error seems to be expected here. On cortex-a15.cortex-a7 the same code executed without errors. So, I wonder, if it's a testcase problem and it should be disabled for CA8? Or maybe it is a compiler bug?