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From: "urjaman at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/57339] [SH] Wrong ISR FPU register save/restore
Date: Sun, 24 Nov 2013 13:30:00 -0000 [thread overview]
Message-ID: <bug-57339-4-2j5aJzovls@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-57339-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57339
Urja Rannikko <urjaman at gmail dot com> changed:
What |Removed |Added
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CC| |urjaman at gmail dot com
--- Comment #2 from Urja Rannikko <urjaman at gmail dot com> ---
(In reply to Oleg Endo from comment #0)
> On SH2A and SH2E R0 is not a banked register and must be pushed before
> dealing with the FP regs.
This is false for atleast SH2A, that is, r0 is a banked register on SH2A.
I dont know about SH2E.
A small quote from the sh2a software manual (2.2.6 Register Banks) (Rev 3.00):
"For the nineteen 32-bit registers comprising general registers R0 to R14,
control register GBR, and system registers MACH, MACL, and PR, high-speed
register saving and restoration can be carried out using a register bank. "
next prev parent reply other threads:[~2013-11-24 13:30 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <bug-57339-4@http.gcc.gnu.org/bugzilla/>
2013-05-20 23:02 ` kkojima at gcc dot gnu.org
2013-11-24 13:30 ` urjaman at gmail dot com [this message]
2013-11-24 14:32 ` olegendo at gcc dot gnu.org
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