[Bug target/57339] [SH] Wrong ISR FPU register save/restore

[Bug target/57339] [SH] Wrong ISR FPU register save/restore

[kkojima at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57339

--- Comment #1 from Kazumoto Kojima <kkojima at gcc dot gnu.org> ---
(In reply to Oleg Endo from comment #0)
> One idea for now would be to emit fixed ISR prologue / epilogue asm blocks
> that deal with the FP regs, if FP regs need to be saved/restored for an ISR.

This would be fine.  I guess that the most important thing with compiler
generated interrupt routine would be its correctness and robustness, not
efficiency.

[Bug target/57339] [SH] Wrong ISR FPU register save/restore

[urjaman at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57339

Urja Rannikko <urjaman at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |urjaman at gmail dot com

--- Comment #2 from Urja Rannikko <urjaman at gmail dot com> ---
(In reply to Oleg Endo from comment #0)
> On SH2A and SH2E R0 is not a banked register and must be pushed before
> dealing with the FP regs.
This is false for atleast SH2A, that is, r0 is a banked register on SH2A.
I dont know about SH2E.

A small quote from the sh2a software manual (2.2.6 Register Banks) (Rev 3.00):
"For the nineteen 32-bit registers comprising general registers R0 to R14,
control register GBR, and system registers MACH, MACL, and PR, high-speed
register saving and restoration can be carried out using a register bank. "

[Bug target/57339] [SH] Wrong ISR FPU register save/restore

[olegendo at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57339

--- Comment #3 from Oleg Endo <olegendo at gcc dot gnu.org> ---
(In reply to Urja Rannikko from comment #2)
> (In reply to Oleg Endo from comment #0)
> > On SH2A and SH2E R0 is not a banked register and must be pushed before
> > dealing with the FP regs.
> This is false for atleast SH2A, that is, r0 is a banked register on SH2A.
> I dont know about SH2E.
> 
> A small quote from the sh2a software manual (2.2.6 Register Banks) (Rev
> 3.00):
> "For the nineteen 32-bit registers comprising general registers R0 to R14,
> control register GBR, and system registers MACH, MACL, and PR, high-speed
> register saving and restoration can be carried out using a register bank. "

Thanks for pointing this out.
It is true that SH2A has register banks.  However, initially register banks are
initially disabled on SH2A and can be enabled at runtime using the Bank Control
Register.
This is different from the SH3/SH4 R0..R7 register bank, which is always
switched when entering an ISR.  Actually, on SH3/SH4 register contents are not
copied but the currently active bank is flipped.

GCC supports the 'resbank' function attribute for utilizing SH2A register
banks, but it's not done by default for ISRs.  Thus, if an ISR doesn't have the
'resbank' attribute specified, R0 can be assumed to be a non-banked register
also on SH2A.

SH2E is basically an SH2 with a single precision FPU.  It doesn't have register
banks.