[Bug rtl-optimization/57462] ira-costs considers only a single register at a time

[Bug rtl-optimization/57462] ira-costs considers only a single register at a time

[vmakarov at redhat dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57462

Vladimir Makarov <vmakarov at redhat dot com> changed:

           What    |Removed                     |Added
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                 CC|                            |vmakarov at redhat dot com

--- Comment #1 from Vladimir Makarov <vmakarov at redhat dot com> ---
  Thanks for the analysis.  That would be an interesting problem to solve.
Although I don't know when I could start work on the problem.

  The code you are mentioning is actually adaptation of code from old regclass
pass which existed since day 1 of GCC. The optimal solution of the problem
might be NP-complete (I am not sure about it, but at least long time ago I
tried to describe it by ILP).

  I should say that even the current cost code is very expensive and speeding
up is on my list to do.  Better solution (through better heuristics) probably
will be even more expensive.  IMHO, it is also GCC specific problem because GCC
postpones code selection (usually compilers do complete code selection before
RA, e.g. selecting insn for add in this case) and that is a consequence of GCC
machine description model.  Doing complete code selection before RA is also
challenging task.

  In any case, the problem is known and quite interesting.  There are a lot of
different approaches to solve it (some require even GCC architectural changes),
none of them are easy.  So I don't think, the problem will be solved soon. 
Sorry.

[Bug rtl-optimization/57462] ira-costs considers only a single register at a time

[josh.m.conner at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57462

--- Comment #2 from Joshua Conner <josh.m.conner at gmail dot com> ---
No problem - I appreciate you taking the time to respond.  This has a
noticeable impact on codegen for ARM because of the redundancy in the CPU/FPU
functionality and cost of transferring data between integer/FP registers, so I
thought it would be worth mentioning in case it wasn't recognized already. 
Thanks.

[Bug rtl-optimization/57462] ira-costs considers only a single register at a time

[ramana at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57462

Ramana Radhakrishnan <ramana at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |ramana at gcc dot gnu.org

--- Comment #3 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
This is part of the reason why on trunk we currently disable 64 bit arithmetic
in neon in a large number of cases. It's sometimes just not worth it -
Additionally neon doesn't have comparison operations so many times one has
noticed that we keep doing a lot of operations on the neon side and then you
just have to move back to the integer side to the comparisons. So there are
times when this doesn't happen properly. 

Ramana

[Bug rtl-optimization/57462] ira-costs considers only a single register at a time

[ramana at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57462

Ramana Radhakrishnan <ramana at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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             Target|arm                         |arm, aarch64
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2015-01-23
     Ever confirmed|0                           |1

--- Comment #4 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
This probably applies to A64 as well where we need to choose between the GP and
the SIMD registers for some of the SISD type operations.