From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26060 invoked by alias); 3 Jun 2013 21:04:44 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 26022 invoked by uid 48); 3 Jun 2013 21:04:39 -0000 From: "wmi at google dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/57518] New: Redundent insn generated in LRA Date: Mon, 03 Jun 2013 21:04:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 4.9.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: wmi at google dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2013-06/txt/msg00136.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57518 Bug ID: 57518 Summary: Redundent insn generated in LRA Product: gcc Version: 4.9.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: wmi at google dot com Testcase: char ip[10]; int total, total1; void foo() { int t; t = ip[2]; total = t & 0x3; } Target: x86_64-linux-gnu gcc version 4.9.0 20130529 (experimental) (GCC) ~/workarea/gcc-r199418/build/install/bin/gcc -O2 -S 1.c .cfi_startproc movzbl ip+2(%rip), %eax movb %al, -16(%rsp) ==> redundent movl -16(%rsp), %eax ==> redundent andl $3, %eax movl %eax, total(%rip) ret .cfi_endproc Target: x86_64-linux-gnu gcc version 4.8.0 20120613 (experimental) (GCC) gcc -O2 -S 1.c .cfi_startproc movzbl ip+2(%rip), %eax andl $3, %eax movl %eax, total(%rip) ret .cfi_endproc IR before LRA: (insn 12 7 8 2 (set (reg:QI 64 [ ip+2 ]) (mem/j/c:QI (const:DI (plus:DI (symbol_ref:DI ("ip") ) (const_int 2 [0x2]))) [0 ip+2 S1 A8])) 1.c:9 87 {*movqi_internal} (expr_list:REG_EQUIV (mem/j/c:QI (const:DI (plus:DI (symbol_ref:DI ("ip") ) (const_int 2 [0x2]))) [0 ip+2 S1 A8]) (nil))) (insn 8 12 9 2 (parallel [ (set (reg:SI 65 [ D.1731 ]) (and:SI (subreg:SI (reg:QI 64 [ ip+2 ]) 0) (const_int 3 [0x3]))) (clobber (reg:CC 17 flags)) ]) 1.c:9 387 {*andsi_1} (expr_list:REG_DEAD (reg:QI 64 [ ip+2 ]) (expr_list:REG_UNUSED (reg:CC 17 flags) (expr_list:REG_EQUIV (mem/c:SI (symbol_ref:DI ("total") ) [2 total+0 S4 A32]) (nil))))) IR after LRA: (insn 12 7 14 2 (set (reg:QI 0 ax [orig:64 ip+2 ] [64]) (mem/j/c:QI (const:DI (plus:DI (symbol_ref:DI ("ip") ) (const_int 2 [0x2]))) [0 ip+2 S1 A8])) 1.c:9 87 {*movqi_internal} (expr_list:REG_EQUIV (mem/j/c:QI (const:DI (plus:DI (symbol_ref:DI ("ip") ) (const_int 2 [0x2]))) [0 ip+2 S1 A8]) (nil))) (insn 14 12 15 2 (set (mem/c:QI (plus:DI (reg/f:DI 7 sp) (const_int -16 [0xfffffffffffffff0])) [3 %sfp+-16 S1 A64]) (reg:QI 0 ax [orig:64 ip+2 ] [64])) 1.c:9 87 {*movqi_internal} (expr_list:REG_DEAD (reg:QI 0 ax [orig:64 ip+2 ] [64]) (nil))) (insn 15 14 8 2 (set (reg:SI 0 ax [orig:65 D.1731 ] [65]) (mem/c:SI (plus:DI (reg/f:DI 7 sp) (const_int -16 [0xfffffffffffffff0])) [3 %sfp+-16 S4 A64])) 1.c:9 85 {*movsi_internal} (nil)) (insn 8 15 16 2 (parallel [ (set (reg:SI 0 ax [orig:65 D.1731 ] [65]) (and:SI (reg:SI 0 ax [orig:65 D.1731 ] [65]) (const_int 3 [0x3]))) (clobber (reg:CC 17 flags)) ]) 1.c:9 387 {*andsi_1} (expr_list:REG_EQUIV (mem/c:SI (symbol_ref:DI ("total") ) [2 total+0 S4 A32]) (nil))) IRA Trace: Pass 0 for finding pseudo/allocno costs a0 (r65,l0) best GENERAL_REGS, allocno GENERAL_REGS a1 (r64,l0) best NO_REGS, allocno NO_REGS a1's rclass are all NO_REGS because it has REG_EQUIV note (equivalent to mem ip+2) Because reg 64 is marked as equivalent to mem ip+2, insn 12 is expected to be deleted and reg 64 in insn 8 replaced by mem ip+2. In LRA constraints, insn 12 is not deleted because the subreg op in insn 8 (see lra-constraints.c:3662 r199418). In addition, reg 64's rclass is NO_REGS, so redundent spills are inserted. The mode size check (lra-constraints.c:3662 r199418) needs to be considered in update_equiv_regs in IRA, in order not to mark the reg 64 equivalent with mem ip + 2 in this case.