From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8270 invoked by alias); 22 Aug 2013 14:03:50 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 8245 invoked by uid 48); 22 Aug 2013 14:03:49 -0000 From: "rearnsha at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/58166] ARMv5: poor register allocation in function containing smull instruction Date: Thu, 22 Aug 2013 14:03:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 4.9.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: rearnsha at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2013-08/txt/msg01157.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166 Richard Earnshaw changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |rearnsha at gcc dot gnu.org, | |vmakarov at redhat dot com --- Comment #4 from Richard Earnshaw --- Vlad, Would you mind commenting on this please? I suspect it's related to the fact that REG_ALLOC_ORDER on ARM is {r3, r2, r1, r0, IP, LR, r4, ...} Which is done to encourage register allocation to use the argument registers that are least likely to be used for parameters. What seems to happen is that the compiler picks r3 and r4 over r2 and r3, even though r4 is a callee saved register and r2 is unused. Is IRA handling the cost of additional registers for multi-reg pseduos correctly?