From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31556 invoked by alias); 16 Sep 2013 10:28:42 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 31529 invoked by uid 48); 16 Sep 2013 10:28:38 -0000 From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/58416] Incorrect x87-based union copying code Date: Mon, 16 Sep 2013 10:28:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 4.6.3 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cf_gcctarget Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2013-09/txt/msg01129.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58416 Richard Biener changed: What |Removed |Added ---------------------------------------------------------------------------- Target| |i?86-*-* --- Comment #2 from Richard Biener --- It is SRA that transforms MCOp.DoubleVal = 0.0; MCOp.IntVal = Val_3(D); *dest_5(D) = MCOp; into MCOp$DoubleVal_7 = 0.0; _8 = VIEW_CONVERT_EXPR(Val_3(D)); MCOp$DoubleVal_4 = _8; MEM[(union MyClass *)dest_5(D)] = MCOp$DoubleVal_4; simplifying into _6 = VIEW_CONVERT_EXPR(Val_3(D)); MEM[(union MyClass *)dest_4(D)] = _6; and (insn 7 6 0 (set (mem:DF (reg/v/f:SI 60 [ dest ]) [0 MEM[(union MyClass *)dest_4(D)]+0 S8 A32]) (subreg:DF (reg/v:DI 61 [ Val ]) 0)) t.C:15 -1 (nil)) causes a reload: (insn 7 11 12 2 (set (reg:DF 8 st [62]) (mem/c:DF (plus:SI (reg/f:SI 7 sp) (const_int 8 [0x8])) [0 Val+0 S8 A32])) t.C:15 134 {*movdf_internal} (nil)) (insn 12 7 0 2 (set (mem:DF (reg/v/f:SI 0 ax [orig:60 dest ] [60]) [0 MEM[(union MyClass *)dest_4(D)]+0 S8 A32]) (reg:DF 8 st [62])) t.C:15 134 {*movdf_internal} (expr_list:REG_DEAD (reg:DF 8 st [62]) (expr_list:REG_DEAD (reg/v/f:SI 0 ax [orig:60 dest ] [60]) (nil)))) where *movdf_internal simply doesn't properly preserve sNaN. It looks wrong for DFmode move instructions to not preserve a IEEE defined flag. I suppose it would be also wrong to not preserve the exact bit pattern (think of canonicalizing NaNs).