[Bug rtl-optimization/59317] [4.9 Regression] [LRA,MIPS] ICE: in check_rtl, at lra.c (insn does not satisfy constraints)

["vmakarov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59317

--- Comment #3 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Robert Suchanek from comment #2)
> The latest patches do not seem to resolve the issue.
> 
> Although the newly generated pseudos get ALL_REGS class assigned, the class
> change does not happen later. As the class is not changed, hard regs are
> found basing on the class, and hence, wrong hard reg(s) are assigned and it
> is found by the coherency check.
> 
> If I'm right, there are least two opportunities where the class can be
> changed in the constraint pass. One fails as the constraints cannot
> influence the classes of the new pseudos (for reload insns) and another one
> when it tries to narrow the class for input pseudos.

Sorry, I can not reproduce this. I built cc1 from yesterday trunk on x86-64
using --target=mips16-linux and then I use -O2 -mips32 -mips16 to compile the
test.  It was ok.

I used the below patch.  You can send me the LRA dump.  May be it will give me
a hint what is going on.

Index: gcc/config/mips/constraints.md
===================================================================
--- gcc/config/mips/constraints.md      (revision 205647)
+++ gcc/config/mips/constraints.md      (working copy)
@@ -19,7 +19,7 @@

 ;; Register constraints

-(define_register_constraint "d" "BASE_REG_CLASS"
+(define_register_constraint "d" "ADDR_REG_CLASS"
   "An address register.  This is equivalent to @code{r} unless
    generating MIPS16 code.")

Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c      (revision 205647)
+++ gcc/config/mips/mips.c      (working copy)
@@ -2157,7 +2157,7 @@
      All in all, it seems more consistent to only enforce this restriction
      during and after reload.  */
   if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
-    return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) ==
8;
+    return  GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;

   return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
 }
@@ -17301,7 +17301,7 @@
       fixed_regs[26] = call_used_regs[26] = 1;
       fixed_regs[27] = call_used_regs[27] = 1;
       fixed_regs[30] = call_used_regs[30] = 1;
-      if (optimize_size)
+      if (optimize_size && !targetm.lra_p())
        {
          fixed_regs[8] = call_used_regs[8] = 1;
          fixed_regs[9] = call_used_regs[9] = 1;
@@ -18699,6 +18699,21 @@
   else
     return default_case_values_threshold ();
 }
+
+static reg_class_t
+mips_spill_class (reg_class_t rclass, enum machine_mode mode)
+{
+  if (TARGET_MIPS16)
+   return SPILL_REGS;
+  return NO_REGS;
+}
+
+static bool
+mips_lra_p (void)
+{
+  return !TARGET_RELOAD;
+}
+
 ^L
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
@@ -18933,6 +18948,15 @@
 #undef TARGET_CASE_VALUES_THRESHOLD
 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold

+#undef TARGET_SPILL_CLASS
+#define TARGET_SPILL_CLASS mips_spill_class
+
+#undef TARGET_LRA_P
+#define TARGET_LRA_P mips_lra_p
+
+#undef TARGET_DIFFERENT_ADDR_DISPLACEMENT_P
+#define TARGET_DIFFERENT_ADDR_DISPLACEMENT_P hook_bool_void_true
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 ^L
 #include "gt-mips.h"
Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h      (revision 205647)
+++ gcc/config/mips/mips.h      (working copy)
@@ -1874,10 +1874,12 @@
 {
   NO_REGS,                     /* no registers in set */
   M16_REGS,                    /* mips16 directly accessible registers */
+  M16F_REGS,                   /* mips16 + frame */
   T_REG,                       /* mips16 T register ($24) */
   M16_T_REGS,                  /* mips16 registers plus T register */
   PIC_FN_ADDR_REG,             /* SVR4 PIC function address register */
   V1_REG,                      /* Register $v1 ($3) used for TLS access.  */
+  SPILL_REGS,                  /* All but $sp and call preserved regs are in
here */
   LEA_REGS,                    /* Every GPR except $25 */
   GR_REGS,                     /* integer registers */
   FP_REGS,                     /* floating point registers */
@@ -1911,10 +1913,12 @@
 {                                                                      \
   "NO_REGS",                                                           \
   "M16_REGS",                                                          \
+  "M16F_REGS",                                                         \
   "T_REG",                                                             \
   "M16_T_REGS",                                                               
\
   "PIC_FN_ADDR_REG",                                                   \
   "V1_REG",                                                            \
+  "SPILL_REGS",                                                               
\
   "LEA_REGS",                                                          \
   "GR_REGS",                                                           \
   "FP_REGS",                                                           \
@@ -1951,10 +1955,12 @@
 {                                                                             
                        \
   { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* NO_REGS */           \
   { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* M16_REGS */          \
+  { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* M16F_REGS */         \
   { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* T_REG */             \
   { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* M16_T_REGS */        \
   { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* PIC_FN_ADDR_REG */   \
   { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* V1_REG */            \
+  { 0x0003fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* SPILL_REGS */        \
   { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* LEA_REGS */          \
   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* GR_REGS */           \
   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 
/* FP_REGS */           \
@@ -1987,8 +1993,10 @@
    valid base register must belong.  A base register is one used in
    an address which is the register value plus a displacement.  */

-#define BASE_REG_CLASS  (TARGET_MIPS16 ? M16_REGS : GR_REGS)
+#define BASE_REG_CLASS  (TARGET_MIPS16 ? M16F_REGS : GR_REGS)

+#define ADDR_REG_CLASS  (TARGET_MIPS16 ? M16_REGS : GR_REGS)
+
 /* A macro whose definition is the name of the class to which a
    valid index register must belong.  An index register is one used
    in an address where its value is either multiplied by a scale
Index: gcc/config/mips/mips.opt
===================================================================
--- gcc/config/mips/mips.opt    (revision 205647)
+++ gcc/config/mips/mips.opt    (working copy)
@@ -380,6 +380,10 @@
 Target Report Mask(SYNCI)
 Use synci instruction to invalidate i-cache

+mreload
+Target Report Var(TARGET_RELOAD)
+Use reload instead of lra
+
 mtune=
 Target RejectNegative Joined Var(mips_tune_option) ToLower
Enum(mips_arch_opt_value)
 -mtune=PROCESSOR       Optimize the output for PROCESSOR