[Bug target/59767] __atomic_load_n with __ATOMIC_SEQ_CST should result in a memory barrier

["amacleod at redhat dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59767

--- Comment #6 from Andrew Macleod <amacleod at redhat dot com> ---
The standard doesn't define what machines should generate what code. It defines
terms for observing effects that need to be adhered to. Their machine model was
created over a few years during the early stages of the memory model to help
observe and test those effects. To the best of our knowledge we think the
results from this model are an efficient and correct implementation within the
standards definition.

If you can provide a test case which demonstrates that this is not a correct
implementation based on observable effects (ie the load is observed out of
order somewhere), then we'd look at fixing it in GCC.

If you want to discuss whether parts are or aren't compliant without a test
case that fails, then you should contact the authors with your questions since
they can give you a far better answer than I ever could.