From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28788 invoked by alias); 16 Jan 2014 04:10:17 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 28668 invoked by uid 48); 16 Jan 2014 04:10:12 -0000 From: "terry.guo at arm dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/59826] ICE caused by mishandling PLD rtx on ARM cortex-m4 target Date: Thu, 16 Jan 2014 04:10:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 4.8.3 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: terry.guo at arm dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2014-01/txt/msg01645.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59826 --- Comment #1 from Terry Guo --- As discussed in http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00875.html, the root cause should be incorrect insn type of preload instruction. 4.8 assigns alu type attribute to preload insn which causes other optimization passes think it can cause data dependence between alu->load/store. The trunk gcc with patch http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00322.html, correctly assign load1 insn type to preload instruction, which avoids the check of data dependence between alu->load/store, thereby no such issue. So the best way to fix this issue in 4.8 is to back port the patch to assign the proper insn type attribute.