From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7861 invoked by alias); 28 Jan 2014 16:20:05 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 7808 invoked by uid 48); 28 Jan 2014 16:20:02 -0000 From: "ubizjak at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/59968] Unused BT patterns Date: Tue, 28 Jan 2014 16:20:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 4.9.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: ubizjak at gmail dot com X-Bugzilla-Status: NEW X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2014-01/txt/msg02905.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D59968 --- Comment #3 from Uro=C5=A1 Bizjak --- (In reply to H.J. Lu from comment #0) > There are some BT patterns in i386 guarded with > TARGET_USE_BT. But there are no testcases to show > if they are used at all. testsuite/gcc.target/i386/bt-*.c > Also BT instructions supports memory destination. > But BT patterns only allow register destination. bt with a memory operand is slow. The bitpos argument is not limited to ope= rand size, and is primarily used for locked memory access. BTW: $ objdump -d cc1 | grep "bt " | wc -l 1228 >>From gcc-bugs-return-441765-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Tue Jan 28 16:23:25 2014 Return-Path: Delivered-To: listarch-gcc-bugs@gcc.gnu.org Received: (qmail 10293 invoked by alias); 28 Jan 2014 16:23:25 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Delivered-To: mailing list gcc-bugs@gcc.gnu.org Received: (qmail 10246 invoked by uid 55); 28 Jan 2014 16:23:21 -0000 From: "hjl at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/59672] Add -m16 support for x86 Date: Tue, 28 Jan 2014 16:23:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 4.9.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: enhancement X-Bugzilla-Who: hjl at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2014-01/txt/msg02907.txt.bz2 Content-length: 2117 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59672 --- Comment #8 from hjl at gcc dot gnu.org --- Author: hjl Date: Tue Jan 28 16:22:45 2014 New Revision: 207196 URL: http://gcc.gnu.org/viewcvs?rev=207196&root=gcc&view=rev Log: Add -m16 support for x86 The .code16gcc directive was added to binutils back in 1999: --- '.code16gcc' provides experimental support for generating 16-bit code from gcc, and differs from '.code16' in that 'call', 'ret', 'enter', 'leave', 'push', 'pop', 'pusha', 'popa', 'pushf', and 'popf' instructions default to 32-bit size. This is so that the stack pointer is manipulated in the same way over function calls, allowing access to function parameters at the same stack offsets as in 32-bit mode. '.code16gcc' also automatically adds address size prefixes where necessary to use the 32-bit addressing modes that gcc generates. --- It encodes 32-bit assembly instructions generated by GCC in 16-bit format so that GCC can be used to generate 16-bit instructions. To do that, the .code16gcc directive must be placed at the very beginning of the assembly code. This patch adds -m16 to x86 backend by: 1. Add -m16 and make it mutually exclusive with -m32, -m64 and -mx32. 2. Treat -m16 like -m32 so that --32 is passed to assembler. 3. Output .code16gcc at the very beginning of the assembly code. 4. Turn off 64-bit ISA when -m16 is used. PR target/59672 * config/i386/gnu-user64.h (SPEC_32): Add "m16|" to "m32". (SPEC_X32): Likewise. (SPEC_64): Likewise. * config/i386/i386.c (ix86_option_override_internal): Turn off OPTION_MASK_ISA_64BIT, OPTION_MASK_ABI_X32 and OPTION_MASK_ABI_64 for TARGET_16BIT. (x86_file_start): Output .code16gcc for TARGET_16BIT. * config/i386/i386.h (TARGET_16BIT): New macro. (TARGET_16BIT_P): Likewise. * config/i386/i386.opt: Add m16. * doc/invoke.texi: Document -m16. Modified: trunk/gcc/ChangeLog trunk/gcc/config/i386/gnu-user64.h trunk/gcc/config/i386/i386.c trunk/gcc/config/i386/i386.h trunk/gcc/config/i386/i386.opt trunk/gcc/doc/invoke.texi