[Bug c/60759] -Wlogical-op should perhaps warn about two-way implicit conversions

["manu at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60759

Manuel López-Ibáñez <manu at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |manu at gcc dot gnu.org

--- Comment #2 from Manuel López-Ibáñez <manu at gcc dot gnu.org> ---
(In reply to Marek Polacek from comment #1)
> We could perhaps implement clang's -Wconstant-logical-operand, but I must
> say I don't like it very much.

So work on something that you like, there so much to do in GCC, that you can be
choosy ;-) In particular, Wlogical-op is not enabled by Wextra because of some
known bugs. If those were fixed it would be extremely more useful than adding
more stuff to it.

What does Wconstant-logical-operand do?
>From gcc-bugs-return-448298-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Fri Apr 04 15:03:20 2014
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Subject: [Bug target/60203] Support long double/_Decimal128 direct move on power8
Date: Fri, 04 Apr 2014 15:03:00 -0000
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id`203

--- Comment #8 from Bill Schmidt <wschmidt at gcc dot gnu.org> ---
Author: wschmidt
Date: Fri Apr  4 15:02:38 2014
New Revision: 209111

URL: http://gcc.gnu.org/viewcvs?rev 9111&root=gcc&view=rev
Log:
[gcc]

2014-04-04  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

    Backport from mainline r207699.
    2014-02-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

    PR target/60137
    * config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter
    for VSX/Altivec vectors that land in GPR registers.

    Backport from mainline r207808.
    2014-02-15  Michael Meissner  <meissner@linux.vnet.ibm.com>

    PR target/60203
    * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints.
    (mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves
    into 64-bit and 32-bit moves.  On 64-bit moves, add support for
    using direct move instructions on ISA 2.07.  Also adjust
    instruction length for 64-bit.
    (mov<mode>_64bit, TFmode/TDmode): Likewise.
    (mov<mode>_32bit, TFmode/TDmode): Likewise.

    Backport from mainline r207868.
    2014-02-18  Michael Meissner  <meissner@linux.vnet.ibm.com>

    PR target/60203
    * config/rs6000/rs6000.md (mov<mode>_64bit, TF/TDmode moves):
    Split 64-bit moves into 2 patterns.  Do not allow the use of
    direct move for TDmode in little endian, since the decimal value
    has little endian bytes within a word, but the 64-bit pieces are
    ordered in a big endian fashion, and normal subreg's of TDmode are
    not allowed.
    (mov<mode>_64bit_dm): Likewise.
    (movtd_64bit_nodm): Likewise.

[gcc/testsuite]

2014-04-04  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

    Backport from mainline r207699.
    2014-02-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

    PR target/60137
    * gcc.target/powerpc/pr60137.c: New file.

    Backport from mainline r207808.
    2014-02-15  Michael Meissner  <meissner@linux.vnet.ibm.com>

    PR target/60203
    * gcc.target/powerpc/pr60203.c: New testsuite.


Added:
    branches/gcc-4_8-branch/gcc/testsuite/gcc.target/powerpc/pr60137.c
    branches/gcc-4_8-branch/gcc/testsuite/gcc.target/powerpc/pr60203.c
Modified:
    branches/gcc-4_8-branch/gcc/ChangeLog
    branches/gcc-4_8-branch/gcc/config/rs6000/rs6000.md
    branches/gcc-4_8-branch/gcc/testsuite/ChangeLog