[Bug target/61051] New: Duplicated instructions in both conditional branches

["carrot at google dot com" <gcc-bugzilla@gcc.gnu.org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=61051

            Bug ID: 61051
           Summary: Duplicated instructions in both conditional branches
           Product: gcc
           Version: 4.10.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: carrot at google dot com
            Target: powerpc64le-grtev4-linux-gnu

Source code:

extern int* foo1 ( long* );
extern int *foo2 ( long *, long *);
extern void foo3 (long, long);

void bar()
{
    long d, f, x, s, r;
    int *p;

    d = 1;
    if (foo1(&r))
    {
            p = foo2( &d, &x);

            if( x != *p )
                    s = 1;
            else
                    s = 2;

            if( r > 0 )
                    f = 1 + d;
            else
                    f = d;

            foo3 (f, d);
            *p = s;
    }
}


Compile it with options -O2 -m64 -mcpu=power8, gcc generates:


bar:
0:    addis 2,12,.TOC.-0b@ha
    addi 2,2,.TOC.-0b@l
    .localentry    bar,.-bar
    mflr 0
    std 30,-16(1)
    std 31,-8(1)
    li 9,1
    std 0,16(1)
    stdu 1,-80(1)
    addi 3,1,32
    std 9,48(1)
    bl foo1
    nop
    cmpdi 7,3,0
    beq 7,.L1
    addi 3,1,48
    addi 4,1,40
    bl foo2
    nop
    ld 10,40(1)
    li 30,1
    lwa 9,0(3)
    mr 31,3
    cmpd 7,9,10
    beq 7,.L12       // C
    ld 9,32(1)       // A1
    cmpdi 7,9,0      // A2
    ble 7,.L4
.L13:
    ld 4,48(1)
    addi 3,4,1
.L5:
    bl foo3
    nop
    stw 30,0(31)
.L1:
    addi 1,1,80
    ld 0,16(1)
    ld 30,-16(1)
    ld 31,-8(1)
    mtlr 0
    blr
    .p2align 4,,15
.L12:
    ld 9,32(1)       // B1
    li 30,2
    cmpdi 7,9,0      // B2
    bgt 7,.L13
.L4:
    ld 3,48(1)
    mr 4,3
    b .L5
    .long 0
    .byte 0,0,0,1,128,2,0,0
    .size    bar,.-bar


Instruction C is a conditional branch. In both branches A1 and B1 are same
instructions, they can be moved to before C. If we use a different conditional
register, instructions A2 and B2 can also be moved before C.