[Bug target/61202] New: gcc generates invalid sqdmulh instruction

[Bug target/61202] New: gcc generates invalid sqdmulh instruction

[carrot at google dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202

            Bug ID: 61202
           Summary: gcc generates invalid sqdmulh instruction
           Product: gcc
           Version: 4.9.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: carrot at google dot com
            Target: aarch64

Created attachment 32808
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=32808&action=edit
testcase

Attached is reduced preprocessed source code. Compile it with gcc 4.9

aarchobj/gcc/cc1 -fpreprocessed t3.i -quiet -dumpbase t3.i -mlittle-endian
"-mabi=lp64" -auxbase-strip t3.o -Os -o t3.s
as -o t3.o t3.s
t3.s: Assembler messages:
t3.s:14: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh
v4.8h,v0.8h,v16.h[0]'
t3.s:42: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh
v0.8h,v1.8h,v16.h[0]'


The error message is very clear, the last operand of sqdmulh can only be low FP
register.

[Bug target/61202] gcc generates invalid sqdmulh instruction

[carrot at google dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202

--- Comment #1 from Carrot <carrot at google dot com> ---
In arm_neon.h, we have

__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
vqdmulhq_n_s16 (int16x8_t a, int16_t b)
{
  int16x8_t result;
  __asm__ ("sqdmulh %0.8h,%1.8h,%2.h[0]"
           : "=w"(result)
           : "w"(a), "w"(b)
           : /* No clobbers */);
  return result;
}

The register constraint for the last operand of sqdmulh is "w", it means
FP_REGS, the correct constraint should be "x", means FP_LO_REGS.

The trunk has the same problem.

[Bug target/61202] gcc generates invalid sqdmulh instruction

[jgreenhalgh at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202

jgreenhalgh at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2014-05-19
                 CC|                            |jgreenhalgh at gcc dot gnu.org
     Ever confirmed|0                           |1

--- Comment #2 from jgreenhalgh at gcc dot gnu.org ---
I did a pass over these last year (
https://gcc.gnu.org/ml/gcc-patches/2013-09/msg00369.html ), but it looks like I
missed the vqdmulh_n intrinsics. A patch along the same lines would be helpful.

Better yet would be moving these to be RTL intrinsics.

[Bug target/61202] gcc generates invalid sqdmulh instruction

[carrot at google dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202

--- Comment #3 from Carrot <carrot at google dot com> ---
4.8 branch also has the same problem.

[Bug target/61202] gcc generates invalid sqdmulh instruction

[carrot at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202

--- Comment #4 from carrot at gcc dot gnu.org ---
Author: carrot
Date: Wed May 21 20:46:46 2014
New Revision: 210728

URL: http://gcc.gnu.org/viewcvs?rev=210728&root=gcc&view=rev
Log:
    PR target/61202
    * config/aarch64/arm_neon.h (vqdmulh_n_s16): Change the last operand's
    constraint.
    (vqdmulhq_n_s16): Likewise.

Modified:
    branches/gcc-4_9-branch/gcc/ChangeLog
    branches/gcc-4_9-branch/gcc/config/aarch64/arm_neon.h

[Bug target/61202] gcc generates invalid sqdmulh instruction

[java4ada at yahoo dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202

java4ada at yahoo dot com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |java4ada at yahoo dot com

--- Comment #5 from java4ada at yahoo dot com ---
Will this bug cover 4.8.x as well? (or file separate bug for 4.8.x)