[Bug target/61407] Build errors on latest OS X 10.10 Yosemite with Xcode 6 on GCC 4.8.3

["larryv at macports dot org" <gcc-bugzilla@gcc.gnu.org>]

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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61407

--- Comment #37 from Lawrence Velázquez <larryv at macports dot org> ---
Okay, what I said initially was correct. This was the specific change I made.

https://gist.github.com/larryv/9b1cd34a34733c10f734
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From: "zhenqiang.chen at arm dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/63210] New: ira does not select the best register compared with gcc 4.8 for ARM THUMB1
Date: Tue, 09 Sep 2014 05:58:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idc210

            Bug ID: 63210
           Summary: ira does not select the best register compared with
                    gcc 4.8 for ARM THUMB1
           Product: gcc
           Version: 5.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zhenqiang.chen at arm dot com

Here is a case shown ira does not select the best register compared with gcc
4.8 for ARM Cortex-M0 with options:

-Os -mthumb -mcpu=cortex-m0

int foo1 (int c);
int foo2 (int c);

int test (int c)
{
  return (foo1 (c) || foo2 (c));
}

Its rtl is like:

    2: r115:SI=r0:SI
    7: r0:SI=r115:SI
    8: r0:SIÊll [`foo1'] argc:0
    9: r111:SI=r0:SI
    4: r110:SI=0x1
   10: pc={(r111:SI!=0)?L17:pc}
   12: r0:SI=r115:SI
   13: r0:SIÊll [`foo2'] argc:0
   14: r112:SI=r0:SI
   16: {r110:SI=r112:SI!=0;clobber r118:SI;}
   17: L17:
   23: r0:SI=r110:SI

For gcc 4.8, r115 is assigned first, which gets "r4" since

  Allocno a3r115 of GENERAL_REGS(9) has 4 avail. regs  4-7, ...

Then r110 is assigned to "r0". "r0:SI=r110:SI" can be optimized.

But for trunk/4.9, r110 is assigned first. r110 is conflict with r115 and the
confict cost of "r0" is high since "r0" is not in "avail. regs  4-7" for r115.
So r110 is not assigned with "r0".