[Bug rtl-optimization/61572] [4.10 Regression] ICE: in assign_by_spills, at lra-assigns.c:1335

["vmakarov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61572

--- Comment #3 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
When LRA processes insn 17 in BB3 it creates a reload pseudo 101 of DREG class

         Choosing alt 0 in insn 17:  (0) =d  (1) %a  (2) rm  (3) =1
{*smulsi3_highpart_1}
      Creating newreg=101 from oldreg=93, assigning class DREG to r101
      Creating newreg=102 from oldreg=100, assigning class AREG to r102
   17: {r101:SI=trunc(sign_extend(r102:SI)*sign_extend(r94:SI) 0>>0x20);clobber
r102:SI;clobber flags:CC;}
      REG_UNUSED r100:SI
      REG_DEAD r94:SI
      REG_UNUSED flags:CC
      REG_EQUAL trunc(sign_extend(r92:SI)*0x10624dd3 0>>0x20)
    Inserting insn reload before:
   63: r102:SI=r92:SI
    Inserting insn reload after:
   62: r93:SI=r101:SI

but LRA can not to assign dx to pseudo 101 as it already lives through BB 3.

Dump from IRA or passes before it shows:

BB2:
;;  entry block defs     0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16
[argp] 20 [frame] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5]
27 [xmm6] 28 [xmm7] 37 [r8] 38 [\
r9]

;; lr  out       1 [dx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] 83

BB3:
;; lr  in        1 [dx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] 83
;; lr  out       1 [dx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] 83 84

DX lives everywhere.  This info is calculated by DF-infrastructure.

So I think that maintainers of DF-infrastructure should work on this PR from
now on.