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From: "mshawcroft at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/61633] AArch64 SISD ASHR instruction split clobbers input register. Date: Mon, 30 Jun 2014 07:55:00 -0000 [thread overview] Message-ID: <bug-61633-4-pcovQcXURy@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-61633-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61633 --- Comment #1 from mshawcroft at gcc dot gnu.org --- Author: mshawcroft Date: Mon Jun 30 07:54:59 2014 New Revision: 212137 URL: https://gcc.gnu.org/viewcvs?rev=212137&root=gcc&view=rev Log: [AArch64] Fix register clobber in, aarch64_ashr_sisd_or_int_<mode>3 split. PR target/61633 The two split patterns associated with aarch64_ashr_sisd_or_int_<mode>3 split the instruction into a NEG followed by an SHL. The split uses one of the input operands as a scratch register to hold the output of the NEG resulting in register corruption. This patch adjusts the splits to use the output operand as the scratch register. 2014-06-30 Marcus Shawcroft <marcus.shawcroft@arm.com> PR target/61633 * config/aarch64/aarch64.md (*aarch64_ashr_sisd_or_int_<mode>3): Add alternative; make early clobber. Adjust both split patterns to use operand 0 as the working register. Modified: trunk/gcc/ChangeLog trunk/gcc/config/aarch64/aarch64.md
next prev parent reply other threads:[~2014-06-30 7:55 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-06-27 15:46 [Bug target/61633] New: " mshawcroft at gcc dot gnu.org 2014-06-30 7:55 ` mshawcroft at gcc dot gnu.org [this message] 2014-06-30 11:59 ` [Bug target/61633] " mshawcroft at gcc dot gnu.org 2014-06-30 12:00 ` mshawcroft at gcc dot gnu.org 2014-07-01 21:18 ` pinskia at gcc dot gnu.org
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