[Bug rtl-optimization/61801] sched2 miscompiles syscall sequence with -g

["rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61801

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2014-07-16
           Assignee|unassigned at gcc dot gnu.org      |rguenth at gcc dot gnu.org
     Ever confirmed|0                           |1

--- Comment #8 from Richard Biener <rguenth at gcc dot gnu.org> ---
The following fixes it as well, in the scheduler.

Index: gcc/sched-deps.c
===================================================================
--- gcc/sched-deps.c    (revision 212580)
+++ gcc/sched-deps.c    (working copy)
@@ -2713,7 +2713,8 @@ sched_analyze_2 (struct deps_desc *deps,
       break;

     case PREFETCH:
-      if (PREFETCH_SCHEDULE_BARRIER_P (x))
+      if (PREFETCH_SCHEDULE_BARRIER_P (x)
+         && !DEBUG_INSN_P (insn))
        reg_pending_barrier = TRUE_BARRIER;
       /* Prefetch insn contains addresses only.  So if the prefetch
         address has no registers, there will be no dependencies on
@@ -2750,7 +2751,8 @@ sched_analyze_2 (struct deps_desc *deps,
           Consider for instance a volatile asm that changes the fpu rounding
           mode.  An insn should not be moved across this even if it only uses
           pseudo-regs because it might give an incorrectly rounded result.  */
-       if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
+       if ((code != ASM_OPERANDS || MEM_VOLATILE_P (x))
+           && !DEBUG_INSN_P (insn))
          reg_pending_barrier = TRUE_BARRIER;

        /* For all ASM_OPERANDS, we must traverse the vector of input operands.

we then have

;;   --- Region Dependences --- b 12 bb 0 
;;      insn  code    bb   dep  prio  cost   reservation
;;      ----  ----    --   ---  ----  ----   -----------
;;      239    90    12     1     5     1  
athlon-direct,athlon-agu,athlon-store       : 127 123nm 216n 240 
...
;;      122    -1    12     3     0     0   nothing     : 124 123nm 
;;      216    90    12     1     5     3   athlon-direct,athlon-load   : 127
123nm 243 

so the false forward dependence of the store to the debug-insn is gone
and instead a proper dependence on the load is there.

Testing the fix.