[Bug target/62120] New: [ICE] ADDITIONAL_REGISTER_NAMES for [YZ]MMs, regno>8 should be disable in 32-bit

[Bug target/62120] New: [ICE] ADDITIONAL_REGISTER_NAMES for [YZ]MMs, regno>8 should be disable in 32-bit

[kyukhin at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62120

            Bug ID: 62120
           Summary: [ICE] ADDITIONAL_REGISTER_NAMES for [YZ]MMs, regno>8
                    should be disable in 32-bit
           Product: gcc
           Version: 4.10.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: kyukhin at gcc dot gnu.org

Hello,

It seems like ADDITIONAL_REG_NAMES should be checked for given register
availability during compilation.

Here's example.
extern int i;                                                                  
                                      void foo ()
{
  register int mm_var asm ("xmm9") __attribute__((unused));
  i+=++mm_var;                                                                 
                                      }

Gives correct error:
$ ./build-x86_64-linux/prev-gcc/xgcc -B./build-x86_64-linux/prev-gcc
/export/users/kyukhin/gcc/git/gcc/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c
-S -m32 -mno-sse
/export/users/kyukhin/gcc/git/gcc/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c:
In function ‘foo’:
/export/users/kyukhin/gcc/git/gcc/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c:4:16:
error: invalid register name for ‘mm_var’
   register int mm_var asm ("xmm9") __attribute__((unused));

Replacing xmm to ymm:
extern int i;
void foo ()
{
  register int mm_var asm ("ymm9") __attribute__((unused));
  i+=++mm_var;
}

Gives ICE:
$ ./build-x86_64-linux/prev-gcc/xgcc -B./build-x86_64-linux/prev-gcc
/export/users/kyukhin/gcc/git/gcc/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c
-S -m32 -mno-sse
/export/users/kyukhin/gcc/git/gcc/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c:
In function ‘foo’:
/export/users/kyukhin/gcc/git/gcc/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c:6:1:
internal compiler error: Max. number of generated reload insns per insn is
achieved (90)

 }
 ^
Please submit a full bug report,

I suspect because no check against ADDITIONAL_REG_NAMES are performed.
Probably it should be updated in i386.c:ix86_conditional_register_usage ()
>From gcc-bugs-return-458343-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Wed Aug 13 09:38:21 2014
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From: "thopre01 at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/62103] Incorrect folding of bitfield in a union on big endian targets
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idb103

--- Comment #4 from thopre01 at gcc dot gnu.org ---
Author: thopre01
Date: Wed Aug 13 09:37:41 2014
New Revision: 213899

URL: https://gcc.gnu.org/viewcvs?rev!3899&root=gcc&view=rev
Log:
2014-08-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    Backport from mainline
    2014-08-12  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    PR middle-end/62103
    * gimple-fold.c (fold_ctor_reference): Don't fold in presence of
    bitfields, that is when size doesn't match the size of type or the
    size of the constructor.

    gcc/testsuite/
    PR middle-end/62103
    * gcc.c-torture/execute/bitfld-6.c: New test.

Added:
    branches/gcc-4_8-branch/gcc/testsuite/gcc.c-torture/execute/bitfld-6.c
Modified:
    branches/gcc-4_8-branch/gcc/ChangeLog
    branches/gcc-4_8-branch/gcc/gimple-fold.c
    branches/gcc-4_8-branch/gcc/testsuite/ChangeLog

[Bug target/62120] [ICE] ADDITIONAL_REGISTER_NAMES for [YZ]MMs, regno>8 should be disable in 32-bit

[tocarip at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62120

--- Comment #1 from tocarip at gcc dot gnu.org ---
Author: tocarip
Date: Tue Sep 30 16:04:15 2014
New Revision: 215729

URL: https://gcc.gnu.org/viewcvs?rev=215729&root=gcc&view=rev
Log:
Fix PR 62120.

gcc/
2014-09-30  Ilya Tocar  <ilya.tocar@intel.com>

       PR middle-end/62120
       * varasm.c (decode_reg_name_and_count): Check availability for
       registers from ADDITIONAL_REGISTER_NAMES.

testsuite/
2014-09-30  Ilya Tocar  <ilya.tocar@intel.com>

       PR middle-end/62120
       * gcc.target/i386/avx512f-additional-reg-names.c: Use register valid
       in 32-bit mode.
       * gcc.target/i386/pr62120.c: New.


Added:
    trunk/gcc/testsuite/gcc.target/i386/pr62120.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/testsuite/ChangeLog
    trunk/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c
    trunk/gcc/varasm.c