[Bug target/63359] aarch64: 32bit registers in inline asm

["rearnsha at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63359

--- Comment #8 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
(In reply to James Molloy from comment #6)
> Good example, although I might argue slightly pathological.
> 

Agreed, this is somewhat pathological, but I only need to find one valid
counter-example :-)

Furthermore, something similar will be quite common on results.  Eg:

int i, j;
unsigned long r;
asm("add %w0, %w1, %w2" : "=r"(r) : "r"(i), "r"(j));  // zero-extend result.

here we *want* the 64-bit result from the implicit zero-extend of writing the
lower 32 bits.

> So in this case currently, GCC doesn't even implicitly promote the argument,
> just uses it as-is. It seems a very dangerous behaviour to have as default.
> Could there not be a more sensible default and an explicit constraint
> modifier to allow this instead?

One of the things I dislike so much about GCC's inline assembly is that it's
just an exposure to users of an internal API in the compiler.  That makes it
very difficult to say precisely what will happen in all cases and *very* hard
to fix problems with it when it exposes bugs.

I'm not saying I'll never accept a warning for this sort of code; but I'd need
convincing that it won't unduly pessimize real code with no acceptable
work-arounds.