[Bug tree-optimization/63743] New: Thumb1: big regression for float operators by r216728

["zhenqiang.chen at arm dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63743

            Bug ID: 63743
           Summary: Thumb1: big regression for float operators by r216728
           Product: gcc
           Version: 5.0
            Status: UNCONFIRMED
          Severity: critical
          Priority: P3
         Component: tree-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zhenqiang.chen at arm dot com

Created attachment 33887
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=33887&action=edit
test case

Root cause: the fold_stmt swaps the operands, which leads to register shuffle.

commit f619ecaed41d1487091098a0f4fdf4d6ed1fa379
Author: rguenth <rguenth@138bc75d-0d04-0410-961f-82ee72b054a4>
Date:   Mon Oct 27 11:30:23 2014 +0000

    2014-10-27  Richard Biener  <rguenther@suse.de>

        * tree-ssa-forwprop.c: Include tree-cfgcleanup.h and tree-into-ssa.h.
        (lattice): New global.
        (fwprop_ssa_val): New function.
        (fold_all_stmts): Likewise.
        (pass_forwprop::execute): Finally fold all stmts.

        * gcc.dg/tree-ssa/forwprop-6.c: Scan ccp1 dump instead.
        * gcc.dg/strlenopt-8.c: Adjust and XFAIL for non_strict_align
        target due to memcpy inline-expansion.


    git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@216728
138bc75d-0d04-0410-961f-82ee72b054a4

A simplified case is attached.

Options: -mthumb -Os -mcpu=cortex-m0

Before the patch, tree codes like

_20 = _14 + _19;
_21 = _20 * x_13;

After the patch, tree codes like

_20 = _14 + _19;
_21 = x_13 * _20;

Without HARD fpu support, all operators will be changed to function calls. The
assemble codes change like:

Before the patch,
        bl      __aeabi_dadd
        ldr     r2, [sp]
        ldr     r3, [sp, #4]
        /* r0, r1 are reused from the return values of the previous call. */
        bl      __aeabi_dmul

After the patch,
        bl      __aeabi_dadd
        mov     r2, r0
        mov     r3, r1
        ldr     r0, [sp]
        ldr     r1, [sp, #4]
        bl      __aeabi_dmul