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* [Bug target/63808] New: [arm] Invalid register saving in FIQ handler causes register corruption @ 2014-11-10 14:56 Sergey.Belyashov at gmail dot com 2014-11-11 16:35 ` [Bug target/63808] " rearnsha at gcc dot gnu.org ` (4 more replies) 0 siblings, 5 replies; 6+ messages in thread From: Sergey.Belyashov at gmail dot com @ 2014-11-10 14:56 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63808 Bug ID: 63808 Summary: [arm] Invalid register saving in FIQ handler causes register corruption Product: gcc Version: 4.8.2 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: Sergey.Belyashov at gmail dot com I have found strange bug which causes USR-mode register damage after FIQ processing. Fiq handler stores R8 to the stack and loads it to USR-mode registers at return instruction: fiq: sub lr, lr, #4 stmfd sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr} .... ldmfd sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, pc}^ To reproduce use this code: unsigned char a[8][5]; int func1(unsigned port); unsigned func2(unsigned,void*); __attribute__((optimize("Os"),interrupt("FIQ"))) void fiq(void) { static unsigned char b[8]; unsigned char *p = a[0]; for(int i = 0; i < 8; ++i) { unsigned s = func1(i + 0x10000); func2(s, &b[i]); do { if (s & 1) ++*p; ++p; s >>= 1; } while (s != 0x01); } } Compile it using: $ arm-none-eabi-gcc -c -S -std=c99 test_fiq.c I try to create dummy FIQ handler with one instruction, which clobbes R8: __asm__ volatile ("bl 0x12345" : : : "r8"); But compiler creates valid entry/exit code (ignoring R8 in save/restore). $ arm-none-eabi-gcc -v Using built-in specs. COLLECT_GCC=arm-none-eabi-gcc COLLECT_LTO_WRAPPER=/usr/bin/../lib/gcc/arm-none-eabi/4.8.4/lto-wrapper Target: arm-none-eabi Configured with: /build/buildd/gcc-arm-none-eabi-4.8.4.2014q3/src/gcc/configure --target=arm-none-eabi --prefix=/build/buildd/gcc-arm-none-eabi-4.8.4.2014q3/install-native --libexecdir=/build/buildd/gcc-arm-none-eabi-4.8.4.2014q3/install-native/lib --infodir=/build/buildd/gcc-arm-none-eabi-4.8.4.2014q3/install-native/share/doc/gcc-arm-none-eabi/info --mandir=/build/buildd/gcc-arm-none-eabi-4.8.4.2014q3/install-native/share/doc/gcc-arm-none-eabi/man --htmldir=/build/buildd/gcc-arm-none-eabi-4.8.4.2014q3/install-native/share/doc/gcc-arm-none-eabi/html --pdfdir=/build/buildd/gcc-arm-none-eabi-4.8.4.2014q3/install-native/share/doc/gcc-arm-none-eabi/pdf --enable-languages=c,c++ --enable-plugins --disable-decimal-float --disable-libffi --disable-libgomp --disable-libmudflap --disable-libquadmath --disable-libssp --disable-libstdcxx-pch --disable-nls --disable-shared --disable-threads --disable-tls --with-gnu-as --with-gnu-ld --with-newlib --with-headers=yes --with-python-dir=share/gcc-arm-none-eabi --with-sysroot=/build/buildd/gcc-arm-none-eabi-4.8.4.2014q3/install-native/arm-none-eabi --with-host-libstdcxx='-static-libgcc -Wl,-Bstatic,-lstdc++,-Bdynamic -lm' --with-pkgversion='GNU Tools for ARM Embedded Processors' --with-multilib-list=armv6-m,armv7-m,armv7e-m,armv7-r Thread model: single gcc version 4.8.4 20140725 (release) [ARM/embedded-4_8-branch revision 213147] (GNU Tools for ARM Embedded Processors) ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/63808] [arm] Invalid register saving in FIQ handler causes register corruption 2014-11-10 14:56 [Bug target/63808] New: [arm] Invalid register saving in FIQ handler causes register corruption Sergey.Belyashov at gmail dot com @ 2014-11-11 16:35 ` rearnsha at gcc dot gnu.org 2014-11-11 17:00 ` rearnsha at gcc dot gnu.org ` (3 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: rearnsha at gcc dot gnu.org @ 2014-11-11 16:35 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63808 --- Comment #1 from Richard Earnshaw <rearnsha at gcc dot gnu.org> --- What CPU are you running this on? ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/63808] [arm] Invalid register saving in FIQ handler causes register corruption 2014-11-10 14:56 [Bug target/63808] New: [arm] Invalid register saving in FIQ handler causes register corruption Sergey.Belyashov at gmail dot com 2014-11-11 16:35 ` [Bug target/63808] " rearnsha at gcc dot gnu.org @ 2014-11-11 17:00 ` rearnsha at gcc dot gnu.org 2014-11-11 17:11 ` Sergey.Belyashov at gmail dot com ` (2 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: rearnsha at gcc dot gnu.org @ 2014-11-11 17:00 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63808 --- Comment #3 from Richard Earnshaw <rearnsha at gcc dot gnu.org> --- (In reply to Sergey Belyashov from comment #2) > Target is armv4: I use gcc options: -marm -march=armv4 Which doesn't really answer my question. Which *CPU* are you seeing this on? My reading of the Architecture reference manual makes me believe this ought to work. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/63808] [arm] Invalid register saving in FIQ handler causes register corruption 2014-11-10 14:56 [Bug target/63808] New: [arm] Invalid register saving in FIQ handler causes register corruption Sergey.Belyashov at gmail dot com 2014-11-11 16:35 ` [Bug target/63808] " rearnsha at gcc dot gnu.org 2014-11-11 17:00 ` rearnsha at gcc dot gnu.org @ 2014-11-11 17:11 ` Sergey.Belyashov at gmail dot com 2015-01-15 13:30 ` [Bug target/63808] [arm] Extra register saving in FIQ handler ramana at gcc dot gnu.org 2015-01-15 13:31 ` rearnsha at gcc dot gnu.org 4 siblings, 0 replies; 6+ messages in thread From: Sergey.Belyashov at gmail dot com @ 2014-11-11 17:11 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63808 --- Comment #4 from Sergey Belyashov <Sergey.Belyashov at gmail dot com> --- AT91SAM7X256 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/63808] [arm] Extra register saving in FIQ handler 2014-11-10 14:56 [Bug target/63808] New: [arm] Invalid register saving in FIQ handler causes register corruption Sergey.Belyashov at gmail dot com ` (2 preceding siblings ...) 2014-11-11 17:11 ` Sergey.Belyashov at gmail dot com @ 2015-01-15 13:30 ` ramana at gcc dot gnu.org 2015-01-15 13:31 ` rearnsha at gcc dot gnu.org 4 siblings, 0 replies; 6+ messages in thread From: ramana at gcc dot gnu.org @ 2015-01-15 13:30 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63808 Ramana Radhakrishnan <ramana at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Keywords| |missed-optimization Target|ARMv4 |arm Status|UNCONFIRMED |NEW Last reconfirmed| |2015-01-15 CC| |ramana at gcc dot gnu.org Ever confirmed|0 |1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/63808] [arm] Extra register saving in FIQ handler 2014-11-10 14:56 [Bug target/63808] New: [arm] Invalid register saving in FIQ handler causes register corruption Sergey.Belyashov at gmail dot com ` (3 preceding siblings ...) 2015-01-15 13:30 ` [Bug target/63808] [arm] Extra register saving in FIQ handler ramana at gcc dot gnu.org @ 2015-01-15 13:31 ` rearnsha at gcc dot gnu.org 4 siblings, 0 replies; 6+ messages in thread From: rearnsha at gcc dot gnu.org @ 2015-01-15 13:31 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63808 Richard Earnshaw <rearnsha at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Priority|P3 |P4 ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-01-15 13:31 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2014-11-10 14:56 [Bug target/63808] New: [arm] Invalid register saving in FIQ handler causes register corruption Sergey.Belyashov at gmail dot com 2014-11-11 16:35 ` [Bug target/63808] " rearnsha at gcc dot gnu.org 2014-11-11 17:00 ` rearnsha at gcc dot gnu.org 2014-11-11 17:11 ` Sergey.Belyashov at gmail dot com 2015-01-15 13:30 ` [Bug target/63808] [arm] Extra register saving in FIQ handler ramana at gcc dot gnu.org 2015-01-15 13:31 ` rearnsha at gcc dot gnu.org
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