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* [Bug ada/64180] New: PowerPC carry bit improvements
@ 2014-12-04  2:23 segher at gcc dot gnu.org
  2014-12-04 18:38 ` [Bug target/64180] " dje at gcc dot gnu.org
                   ` (9 more replies)
  0 siblings, 10 replies; 11+ messages in thread
From: segher at gcc dot gnu.org @ 2014-12-04  2:23 UTC (permalink / raw)
  To: gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64180

            Bug ID: 64180
           Summary: PowerPC carry bit improvements
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: ada
          Assignee: segher at gcc dot gnu.org
          Reporter: segher at gcc dot gnu.org
            Target: powerpc*-*-*

In current mainline, every RTL instruction that uses XER[CA] (the
carry bit) will have to set it in the same instruction, because
other instructions clobber it at will.  Those RTL insns then are
output as multiple machine insns.  This is bad for multiple
reasons:

1) It leads to code explosion: we have patterns like and_neg_geu.
   None of those are necessary if we can just express the machine
   insns as separate RTL insns directly.
2) There are so many possible combinations that some are missed,
   or deemed not worth the effort (and cost) to implement as RTL
   insns.  This is especially true of the multi-precision add/sub
   patterns.  As a consequence we get not very well optimised
   code.
3) The resulting insns are not scheduled well.

So, let's improve this.


THE PLAN
========
First, we need to let GCC know about the CA bit.  This is done.
GCC thinks the register is SImode or DImode, which is a) fine,
because it will never allocate anything to it itself, and we
write only 0 or 1 to it; and b) handy, because we have to do
arithmetic with it in those modes all the time.

Secondly, we need to change all the patterns that clobber CA
so that either: a) they don't clobber it anymore; or b) the
clobber is explicit.  This is partly done.  Remaining are two
classes of insns: 1) those that should be split into separate
insns; and 2) those that slightly regress code quality if
changed (mostly those use "addic" so they can use GPR0 as
well as all other GPRs).

The insns in 1) are the multi-precision add/sub/neg, and all
the various eq/ne/ltu/gtu/leu/geu things.  These all have to
be done at the same time, using...

Thirdly, we need to add patterns for the actual machine insns.
For things like "addic" we need multiple patterns, one each
per kind of immediate op (pos/neg/0/-1), since canonical RTL
for those is different.

We also should make all asm() clobber CA implicitly, because
quite a lot of code in the field clobbers it without telling
the compiler.

Finally, as a further improvement, we should put some extra
attributes on the "C" and "E" insns so that the scheduling
descriptions can be made more accurate; and those scheduling
descriptions then should be updated.


^ permalink raw reply	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-01-02  2:16 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-12-04  2:23 [Bug ada/64180] New: PowerPC carry bit improvements segher at gcc dot gnu.org
2014-12-04 18:38 ` [Bug target/64180] " dje at gcc dot gnu.org
2014-12-10 18:29 ` segher at gcc dot gnu.org
2014-12-10 18:31 ` segher at gcc dot gnu.org
2014-12-10 18:31 ` segher at gcc dot gnu.org
2014-12-10 18:32 ` segher at gcc dot gnu.org
2014-12-10 18:34 ` segher at gcc dot gnu.org
2014-12-10 18:36 ` segher at gcc dot gnu.org
2014-12-10 18:38 ` segher at gcc dot gnu.org
2014-12-12 21:20 ` pthaugen at gcc dot gnu.org
2015-01-02  2:16 ` segher at gcc dot gnu.org

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