From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28046 invoked by alias); 4 Dec 2014 02:23:04 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 27985 invoked by uid 48); 4 Dec 2014 02:22:53 -0000 From: "segher at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug ada/64180] New: PowerPC carry bit improvements Date: Thu, 04 Dec 2014 02:23:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: ada X-Bugzilla-Version: unknown X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: segher at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: segher at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter cf_gcctarget Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2014-12/txt/msg00433.txt.bz2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64180 Bug ID: 64180 Summary: PowerPC carry bit improvements Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal Priority: P3 Component: ada Assignee: segher at gcc dot gnu.org Reporter: segher at gcc dot gnu.org Target: powerpc*-*-* In current mainline, every RTL instruction that uses XER[CA] (the carry bit) will have to set it in the same instruction, because other instructions clobber it at will. Those RTL insns then are output as multiple machine insns. This is bad for multiple reasons: 1) It leads to code explosion: we have patterns like and_neg_geu. None of those are necessary if we can just express the machine insns as separate RTL insns directly. 2) There are so many possible combinations that some are missed, or deemed not worth the effort (and cost) to implement as RTL insns. This is especially true of the multi-precision add/sub patterns. As a consequence we get not very well optimised code. 3) The resulting insns are not scheduled well. So, let's improve this. THE PLAN ======== First, we need to let GCC know about the CA bit. This is done. GCC thinks the register is SImode or DImode, which is a) fine, because it will never allocate anything to it itself, and we write only 0 or 1 to it; and b) handy, because we have to do arithmetic with it in those modes all the time. Secondly, we need to change all the patterns that clobber CA so that either: a) they don't clobber it anymore; or b) the clobber is explicit. This is partly done. Remaining are two classes of insns: 1) those that should be split into separate insns; and 2) those that slightly regress code quality if changed (mostly those use "addic" so they can use GPR0 as well as all other GPRs). The insns in 1) are the multi-precision add/sub/neg, and all the various eq/ne/ltu/gtu/leu/geu things. These all have to be done at the same time, using... Thirdly, we need to add patterns for the actual machine insns. For things like "addic" we need multiple patterns, one each per kind of immediate op (pos/neg/0/-1), since canonical RTL for those is different. We also should make all asm() clobber CA implicitly, because quite a lot of code in the field clobbers it without telling the compiler. Finally, as a further improvement, we should put some extra attributes on the "C" and "E" insns so that the scheduling descriptions can be made more accurate; and those scheduling descriptions then should be updated.