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From: "kugan at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/64304] AArch64 miscompilation with -mgeneral-regs-only
Date: Mon, 15 Dec 2014 03:27:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64304

kugan at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |kugan at gcc dot gnu.org

--- Comment #1 from kugan at gcc dot gnu.org ---
I haven't looked in detail but and:SI is gone during the combine stage. For
some reason, combine thinks it is OK to  remove and:SI.

Here is the .213r.ud_dce  and .214r.combine when it fails.


 (note 5 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
-(insn 2 5 3 2 (set (reg/v:SI 82 [ bit ])
-        (reg:SI 0 x0 [ bit ])) bug.c:3 38 {*movsi_aarch64}
-     (expr_list:REG_DEAD (reg:SI 0 x0 [ bit ])
-        (nil)))
+(note 2 5 3 2 NOTE_INSN_DELETED)
 (insn 3 2 4 2 (set (reg/v:SI 83 [ value ])
         (zero_extend:SI (reg:QI 1 x1 [ value ]))) bug.c:3 76
{*zero_extendqisi2_aarch64}
      (expr_list:REG_DEAD (reg:QI 1 x1 [ value ])
         (nil)))
 (note 4 3 7 2 NOTE_INSN_FUNCTION_BEG)
-(insn 7 4 8 2 (set (reg:SI 84 [ D.1492 ])
-        (and:SI (reg/v:SI 82 [ bit ])
-            (const_int 7 [0x7]))) bug.c:4 399 {andsi3}
-     (expr_list:REG_DEAD (reg/v:SI 82 [ bit ])
-        (nil)))
+(note 7 4 8 2 NOTE_INSN_DELETED)
 (insn 8 7 9 2 (set (reg:SI 86)
         (const_int 1 [0x1])) bug.c:4 38 {*movsi_aarch64}
      (nil))
-(insn 9 8 10 2 (set (reg:SI 85 [ D.1492 ])
-        (ashift:SI (reg:SI 86)
-            (subreg:QI (reg:SI 84 [ D.1492 ]) 0))) bug.c:4 539
{*aarch64_ashl_sisd_or_int_si3}
-     (expr_list:REG_DEAD (reg:SI 86)
-        (expr_list:REG_DEAD (reg:SI 84 [ D.1492 ])
-            (expr_list:REG_EQUAL (ashift:SI (const_int 1 [0x1])
-                    (subreg:QI (reg:SI 84 [ D.1492 ]) 0))
-                (nil)))))
+(insn 9 8 10 2 (set (reg:QI 85 [ D.1492 ])
+        (ashift:QI (subreg:QI (reg:SI 86) 0)
+            (reg:QI 0 x0 [ bit ]))) bug.c:4 556 {*ashlqi3_insn}
+     (expr_list:REG_DEAD (reg:SI 0 x0 [ bit ])
+        (expr_list:REG_DEAD (reg:SI 86)
+            (nil))))
 (insn 10 9 11 2 (set (reg/v:SI 76 [ mask ])
-        (zero_extend:SI (subreg:QI (reg:SI 85 [ D.1492 ]) 0))) bug.c:4 76
{*zero_extendqisi2_aarch64}
-     (expr_list:REG_DEAD (reg:SI 85 [ D.1492 ])
-        (nil)))
-(insn 11 10 12 2 (set (reg:CC 66 cc)
-        (compare:CC (reg/v:SI 83 [ value ])
-            (const_int 0 [0]))) bug.c:5 330 {*cmpsi}
-     (expr_list:REG_DEAD (reg/v:SI 83 [ value ])
+        (zero_extend:SI (reg:QI 85 [ D.1492 ]))) bug.c:4 76
{*zero_extendqisi2_aarch64}
+     (expr_list:REG_DEAD (reg:QI 85 [ D.1492 ])
         (nil)))
.....