From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18231 invoked by alias); 8 Jan 2015 12:33:40 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 18188 invoked by uid 48); 8 Jan 2015 12:33:34 -0000 From: "pinskia at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated Date: Thu, 08 Jan 2015 12:33:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 5.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: pinskia at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-01/txt/msg00456.txt.bz2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 --- Comment #2 from Andrew Pinski --- (In reply to kugan from comment #1) > According to AAPCS64 > (http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/ > IHI0055C_beta_aapcs64.pdf), the unused parm register bits have "unspecified > value".So I think it is Needed It is not needed because the next instruction has a sign extend and the other uses of the result of the sign extend only use the lower 32bits of the register.