[Bug target/64760] New: [SH] Avoid multiple #imm,r0 insns with the same #imm value

[Bug target/64760] New: [SH] Avoid multiple #imm,r0 insns with the same #imm value

[olegendo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64760

            Bug ID: 64760
           Summary: [SH] Avoid multiple #imm,r0 insns with the same #imm
                    value
           Product: gcc
           Version: 5.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: olegendo at gcc dot gnu.org
            Target: sh*-*-*

In libstdc++ there is code such as:
        mov     r9,r0
        cmp/eq  #-1,r0
        mov     r1,r0
        movt    r2
        cmp/eq  #-1,r0
        movt    r1
        cmp/eq  r1,r2
        bt      ...

It seems that it's better to avoid #imm,r0 insns such as cmp/eq, and, or, xor,
tst, if the #imm value can be shared among several insns.  The insns don't have
to be same, only the constant value.

The above code could be something like:
        mov     #-1,r0
        cmp/eq  r9,r0
        movt    r2
        cmp/eq  r1,r0
        movt    r1
        cmp/eq  r1,r2

Preferably, this should be done before RA to reduce r0 pressure.  It can be
accomplished by simply loading the constant into a pseudo and replacing the
operands in the insns.

On the other hand, if the other operand (other than #imm) is likely to end up
in r0, the #imm,r0 insn is probably going to be better.

A possible metric for 'likely to be in r0' could be:
- the operand is loaded using a mov.{b|w} @(disp,Rn),R0
- the operand is needed in r0 by some other surrounding insns

[Bug target/64760] [SH] Avoid multiple #imm,r0 insns with the same #imm value

[olegendo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64760

Oleg Endo <olegendo at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2015-02-28
     Ever confirmed|0                           |1

--- Comment #1 from Oleg Endo <olegendo at gcc dot gnu.org> ---
Another scenario where #imm,r0 insns could/should be avoided is code such as:
        ...
        mov.b   r0,@(1,r2)
        mov.b   r0,@(2,r2)
        mov.b   r0,@(3,r2)
        mov     r1,r0         <<<<
        tst     #1,r0         <<<<
        bt/s    ...
        mov.b   r0,@(0,r2)

Because before the #imm,r0 insn the r0 reg is used the code is forced to be
sequential.  In the example however, the stores and the test can be
parallelized which would save 1 cycle:

        ...
        mov.b   r0,@(1,r2)
        mov     #1,r3         <<<<
        mov.b   r0,@(2,r2)
        tst     r3,r1         <<<<
        mov.b   r0,@(3,r2)
        bt/s    ...
        mov.b   r0,@(0,r2)