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* [Bug target/64897] Floating-point "and" not optimized on x86-64
[not found] <bug-64897-4@http.gcc.gnu.org/bugzilla/>
@ 2015-02-02 8:45 ` rguenth at gcc dot gnu.org
2021-11-28 6:28 ` pinskia at gcc dot gnu.org
2021-11-28 6:31 ` pinskia at gcc dot gnu.org
2 siblings, 0 replies; 3+ messages in thread
From: rguenth at gcc dot gnu.org @ 2015-02-02 8:45 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64897
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords| |missed-optimization
Target| |x86_64-*-*, i?86-*-*
Status|UNCONFIRMED |NEW
Last reconfirmed| |2015-02-02
Ever confirmed|0 |1
--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
We expand from
fand1 (double x)
{
long unsigned int _2;
long unsigned int ix.1_4;
<bb 2>:
_2 = VIEW_CONVERT_EXPR<long unsigned int>(x_5(D));
ix.1_4 = _2 & 9223372036854775807;
x_3 = VIEW_CONVERT_EXPR<double>(ix.1_4);
return x_3;
so the issue might be as "simple" as that GIMPLE doesn't allow bit operations
on FP operands.
Which makes it a RTL missed optimization (to (and:DF ...)):
(set (reg:DF 90 [ <retval> ])
(subreg:DF (and:DI (subreg:DI (reg/v:DF 91 [ x ]) 0)
(const_int 9223372036854775807 [0x7fffffffffffffff])) 0))
unless RTL has the same restriction.
And/or at target missed optimization in case it doesn't provide a AND
instruction
on DFmode (it doesn't as far as I can see).
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Bug target/64897] Floating-point "and" not optimized on x86-64
[not found] <bug-64897-4@http.gcc.gnu.org/bugzilla/>
2015-02-02 8:45 ` [Bug target/64897] Floating-point "and" not optimized on x86-64 rguenth at gcc dot gnu.org
@ 2021-11-28 6:28 ` pinskia at gcc dot gnu.org
2021-11-28 6:31 ` pinskia at gcc dot gnu.org
2 siblings, 0 replies; 3+ messages in thread
From: pinskia at gcc dot gnu.org @ 2021-11-28 6:28 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64897
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Since GCC 9 we get for fand1:
movq %xmm0, %rax
btrq $63, %rax
movq %rax, %xmm0
ret
The question comes does the movement between sse registers and gprs is cheaper
than the load that and would cause.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Bug target/64897] Floating-point "and" not optimized on x86-64
[not found] <bug-64897-4@http.gcc.gnu.org/bugzilla/>
2015-02-02 8:45 ` [Bug target/64897] Floating-point "and" not optimized on x86-64 rguenth at gcc dot gnu.org
2021-11-28 6:28 ` pinskia at gcc dot gnu.org
@ 2021-11-28 6:31 ` pinskia at gcc dot gnu.org
2 siblings, 0 replies; 3+ messages in thread
From: pinskia at gcc dot gnu.org @ 2021-11-28 6:31 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64897
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |amonakov at gcc dot gnu.org
--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
*** Bug 93039 has been marked as a duplicate of this bug. ***
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-11-28 6:31 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <bug-64897-4@http.gcc.gnu.org/bugzilla/>
2015-02-02 8:45 ` [Bug target/64897] Floating-point "and" not optimized on x86-64 rguenth at gcc dot gnu.org
2021-11-28 6:28 ` pinskia at gcc dot gnu.org
2021-11-28 6:31 ` pinskia at gcc dot gnu.org
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