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From: "enkovich.gnu at gmail dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/65105] [i386] XMM registers are not used for 64bit computations on 32bit target Date: Wed, 18 Feb 2015 13:28:00 -0000 [thread overview] Message-ID: <bug-65105-4-cv4mBNXebc@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-65105-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65105 --- Comment #2 from Ilya Enkovich <enkovich.gnu at gmail dot com> --- For this test I see 'plus' and 'minus' ops have DI mode until RA and get GPR pairs: (insn 12 35 13 2 (parallel [ (set (reg:DI 0 ax [orig:98 D.1945 ] [98]) (plus:DI (reg:DI 0 ax [orig:97 D.1945 ] [97]) (reg:DI 2 cx [orig:96 D.1945 ] [96]))) (clobber (reg:CC 17 flags)) ]) test.c:4 215 {*adddi3_doubleword} (nil)) (insn 13 12 18 2 (parallel [ (set (reg:DI 0 ax [orig:95 D.1945 ] [95]) (minus:DI (reg:DI 0 ax [orig:98 D.1945 ] [98]) (reg/v:DI 4 si [orig:94 z ] [94]))) (clobber (reg:CC 17 flags)) ]) test.c:4 259 {*subdi3_doubleword} (nil)) 'ior' and 'and' use SI mode and subregs starting from expand.
next prev parent reply other threads:[~2015-02-18 13:28 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-02-18 12:11 [Bug target/65105] New: " enkovich.gnu at gmail dot com 2015-02-18 12:45 ` [Bug target/65105] " jakub at gcc dot gnu.org 2015-02-18 13:28 ` enkovich.gnu at gmail dot com [this message] 2015-09-29 9:33 ` ienkovich at gcc dot gnu.org 2015-09-29 9:37 ` ienkovich at gcc dot gnu.org 2022-03-05 8:52 ` cvs-commit at gcc dot gnu.org
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