[Bug target/65167] New: ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx

[Bug target/65167] New: ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65167

            Bug ID: 65167
           Summary: ICE: in assign_by_spills, at lra-assigns.c:1383
                    (unable to find a register to spill) with -O
                    -fschedule-insns -fcheck-pointer-bounds -mmpx
           Product: gcc
           Version: 5.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz

Created attachment 34837
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=34837&action=edit
reduced testcase

Compiler output:
$ gcc -O -fschedule-insns -fcheck-pointer-bounds -mmpx testcase.c
testcase.c: In function 'foo.chkp':
testcase.c:7:1: error: unable to find a register to spill
 }
 ^
testcase.c:7:1: error: this is the insn:
(insn 21 49 32 2 (parallel [
            (unspec [
                    (mem:DI (unspec:DI [
                                (plus:DI (reg/f:DI 7 sp)
                                    (const_int -8 [0xfffffffffffffff8]))
                                (subreg:DI (reg/v/f:DI 94 [ e ]) 0)
                            ] UNSPEC_BNDLDX_ADDR) [0  S8 A8])
                    (reg:BND64 111 [orig:101 __chkp_bounds_of_e ] [101])
                ] UNSPEC_BNDSTX)
            (set (mem/v:BLK (plus:DI (reg/f:DI 7 sp)
                        (const_int -8 [0xfffffffffffffff8])) [0  A8])
                (unspec:BLK [
                        (mem/v:BLK (plus:DI (reg/f:DI 7 sp)
                                (const_int -8 [0xfffffffffffffff8])) [0  A8])
                    ] UNSPEC_MPX_FENCE))
        ]) testcase.c:5 1067 {*bnd64_stx}
     (expr_list:REG_DEAD (reg:BND64 111 [orig:101 __chkp_bounds_of_e ] [101])
        (expr_list:REG_DEAD (reg/v/f:DI 94 [ e ])
            (nil))))
testcase.c:7:1: internal compiler error: in assign_by_spills, at
lra-assigns.c:1383
0xbcd308 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /mnt/svn/gcc-trunk/gcc/rtl-error.c:110
0xac5ef6 assign_by_spills
        /mnt/svn/gcc-trunk/gcc/lra-assigns.c:1383
0xac6723 lra_assign()
        /mnt/svn/gcc-trunk/gcc/lra-assigns.c:1558
0xac2042 lra(_IO_FILE*)
        /mnt/svn/gcc-trunk/gcc/lra.c:2337
0xa705e1 do_reload
        /mnt/svn/gcc-trunk/gcc/ira.c:5418
0xa705e1 execute
        /mnt/svn/gcc-trunk/gcc/ira.c:5589
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <http://gcc.gnu.org/bugs.html> for instructions.

Tested revisions:
r220888 - fail

[Bug target/65167] ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx

[enkovich.gnu at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65167

--- Comment #1 from Ilya Enkovich <enkovich.gnu at gmail dot com> ---
For call arguments we usually store bounds passed in bounds tables and then
fill bounds passed in registers.  But with -fschedule-insns we have order
changed and all hard registers are filled with values before BNDSTX.  This is
not a nice schedule because it requires additional spills.  Seems LRA fails to
spill a register when all of them are used to pass args.  This situation didn't
happen before because bounds registers is the first case when we use all
registers to pass args. Should LRA be able to spill/fill initialized hard reg?
Can it be fixed or we better avoid such scheduling?

[Bug target/65167] ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65167

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ysrumyan at gmail dot com

--- Comment #2 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Ilya Enkovich from comment #1)
> For call arguments we usually store bounds passed in bounds tables and then
> fill bounds passed in registers.  But with -fschedule-insns we have order
> changed and all hard registers are filled with values before BNDSTX.  This
> is not a nice schedule because it requires additional spills.  Seems LRA
> fails to spill a register when all of them are used to pass args.  This
> situation didn't happen before because bounds registers is the first case
> when we use all registers to pass args. Should LRA be able to spill/fill
> initialized hard reg? Can it be fixed or we better avoid such scheduling?

There are a bunch of functions in i386.c (please grep for TARGET_SCHED_REORDER,
TARGET_SCHED_ADJUST_PRIORITY and TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK)
that are intended to solve issues like this. AFAICS, they have to be enhanced
to handle bound registers and to preserve the order of insns involving bound
regs.

I'm adding author of these functions to CC.
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Subject: [Bug target/65167] ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65167

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2015-02-24
   Target Milestone|---                         |5.0
     Ever confirmed|0                           |1

--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
Confirmed.
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Subject: [Bug target/65138] [5 Regression] testsuite ICEs on powerpc64le
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https://gcc.gnu.org/bugzilla/show_bug.cgi?ide138

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
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                   |                            |jakub at gcc dot gnu.org

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Perhaps something is broken in the rs6000 target attribute support (which LTO
now uses for all functions)?
Like, PR61925 fix not ported to rs6000 yet?

[Bug target/65167] ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx

[enkovich.gnu at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65167

--- Comment #4 from Ilya Enkovich <enkovich.gnu at gmail dot com> ---
ix86_function_arg_regno_p doesn't recognize bnd registers as args. Also
avoid_func_arg_motion doesn't work for BNDSTX because it is not a single set.  

This patch works for reproducer:

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 71a5b22..acbe25f 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -6068,6 +6068,9 @@ ix86_function_arg_regno_p (int regno)
   int i;
   const int *parm_regs;

+  if (TARGET_MPX && BND_REGNO_P (regno))
+    return true;
+
   if (!TARGET_64BIT)
     {
       if (TARGET_MACHO)
@@ -26846,6 +26849,16 @@ avoid_func_arg_motion (rtx_insn *first_arg, rtx_insn
*insn)
   rtx set;
   rtx tmp;

+  /* Add anti dependencies for bounds stores.  */
+  if (INSN_P (insn)
+      && GET_CODE (PATTERN (insn)) == PARALLEL
+      && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
+      && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_BNDSTX)
+    {
+      add_dependence (first_arg, insn, REG_DEP_ANTI);
+      return;
+    }
+
   set = single_set (insn);
   if (!set)
     return;


Will run a testing for it.

[Bug target/65167] ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65167

--- Comment #5 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Ilya Enkovich from comment #4)
> ix86_function_arg_regno_p doesn't recognize bnd registers as args. Also
> avoid_func_arg_motion doesn't work for BNDSTX because it is not a single
> set.  
> 
> This patch works for reproducer:

> +  if (TARGET_MPX && BND_REGNO_P (regno))

No need for TARGET_MPX check, there will be no bnd regs when this flag is
cleared.
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https://gcc.gnu.org/bugzilla/show_bug.cgi?ide190

Markus Trippelsdorf <trippels at gcc dot gnu.org> changed:

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--- Comment #1 from Markus Trippelsdorf <trippels at gcc dot gnu.org> ---
Cannot reproduce with grahite enabled 4.9.3 20150224.

[Bug target/65167] ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx

[enkovich.gnu at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65167

--- Comment #6 from Ilya Enkovich <enkovich.gnu at gmail dot com> ---
(In reply to Uroš Bizjak from comment #5)
> (In reply to Ilya Enkovich from comment #4)
> 
> > +  if (TARGET_MPX && BND_REGNO_P (regno))
> 
> No need for TARGET_MPX check, there will be no bnd regs when this flag is
> cleared.

__builtin_apply_args stores all registers that might be used to pass arguments
to a function.  With no target check it will always try to store bounds with no
instructions to do that.
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idd842

--- Comment #3 from Ville Voutilainen <ville.voutilainen at gmail dot com> ---
Email sent to Bjarne.

[Bug target/65167] ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx

[ienkovich at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65167

--- Comment #7 from ienkovich at gcc dot gnu.org ---
Author: ienkovich
Date: Wed Feb 25 15:05:48 2015
New Revision: 220970

URL: https://gcc.gnu.org/viewcvs?rev=220970&root=gcc&view=rev
Log:
gcc/

    PR target/65167
    * gcc/config/i386/i386.c (ix86_function_arg_regno_p): Support
    bounds registers.
    (avoid_func_arg_motion): Add dependencies for BNDSTX insns.

gcc/testsuite/

    PR target/65167
    * gcc.target/i386/pr65167.c: New.


Added:
    trunk/gcc/testsuite/gcc.target/i386/pr65167.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.c
    trunk/gcc/testsuite/ChangeLog

[Bug target/65167] ICE: in assign_by_spills, at lra-assigns.c:1383 (unable to find a register to spill) with -O -fschedule-insns -fcheck-pointer-bounds -mmpx

[ienkovich at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65167

ienkovich at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
                 CC|                            |ienkovich at gcc dot gnu.org
         Resolution|---                         |FIXED

--- Comment #8 from ienkovich at gcc dot gnu.org ---
Fixed