[Bug rtl-optimization/65235] New: [4.8, 4.9, 5 Regression] Simplifying vec_select of vec_concat miscompiles when first element of vec_concat is const_int

["ktkachov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65235

            Bug ID: 65235
           Summary: [4.8, 4.9, 5 Regression] Simplifying vec_select of
                    vec_concat miscompiles when first element of
                    vec_concat is const_int
           Product: gcc
           Version: 5.0
            Status: UNCONFIRMED
          Keywords: wrong-code
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ktkachov at gcc dot gnu.org
            Target: aarch64

This aarch64 intrinsics testcase aborts.

#include "arm_neon.h"

int main (int argc, char** argv)
{
  int64x1_t val1;
  int64x1_t val2;
  int64x1_t val3;
  uint64x1_t val13;
  uint64x2_t val14;
  uint64_t got;
  uint64_t exp;
  val1 = vcreate_s64(UINT64_C(0xffffffff80008000));
  val2 = vcreate_s64(UINT64_C(0x0000f38d00000000));
  val3 = vcreate_s64(UINT64_C(0xffff7fff0000809b));
  //  Expect: "val13" = 8000000000001553
  val13 = vcreate_u64 (UINT64_C(0x8000000000001553));
  //  Expect: "val14" = 0010 0000 0000 0002 0000 0000 0000 0000
  val14 = vcombine_u64(vcgt_s64(vqrshl_s64(val1, val2),
                vshr_n_s64(val3, 18)),
               vshr_n_u64(val13, 11));
  /* Should be 0000000000000000.  */
  got = vgetq_lane_u64(val14, 0);
  exp = 0;
  if(exp != got)
    __builtin_abort ();
}



Investigation shows that the problem is in the simplify-rtx machinery:
Combine tries to combine:
 (insn 72 71 73 2 (set (reg:V2DI 117 [ D.18177 ])
         (vec_concat:V2DI (reg:DI 176 [ D.18179 ])
           (reg:DI 114 [ D.18168 ]))) 
      (expr_list:REG_DEAD (reg:DI 176 [ D.18179 ])
      (expr_list:REG_DEAD (reg:DI 114 [ D.18168 ])

and

 (insn 104 102 105 2 (set (reg:DI 193 [ D.18168 ])
         (vec_select:DI (reg:V2DI 117 [ D.18177 ])
             (parallel [
                     (const_int 0 [0])
                 ])))
      (expr_list:REG_DEAD (reg:V2DI 117 [ D.18177 ])
         (nil)))

but ends up generating:
(set (reg:DI 193 [ D.18168 ])
    (reg:DI 114 [ D.18168 ]))

i.e. it picks element 1 instead of the requested element 0.

This happens during combine where it tries to to simplify a vec_select 0 of the
intermediate rtx:
(vec_concat:V2DI (const_int -1 [0xffffffffffffffff])
    (reg:DI 114 [ D.18166 ]))


The relevant code in simplify-rtx has been there for some time and is broken
for all release branches. I have a patch in testing...