[Bug target/65710] New: [5 Regression] Thumb1 ICE caused by no register to spill

[Bug target/65710] New: [5 Regression] Thumb1 ICE caused by no register to spill

[terry.guo at arm dot com]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="UTF-8", Size: 4180 bytes --]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

            Bug ID: 65710
           Summary: [5 Regression] Thumb1 ICE caused by no register to
                    spill
           Product: gcc
           Version: 5.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: terry.guo at arm dot com

Created attachment 35268
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35268&action=edit
test case

Revision 221867 is the fix to PR65647. But it causes another ICE for thumb1
target as below:

$./install/bin/arm-none-eabi-gcc -mthumb -O2 -S regex.i 
regex.i: In function ‘byte_re_match_2_internal’:
regex.i:10121:1: error: unable to find a register to spill
 }
 ^
regex.i:10121:1: error: this is the insn:
(insn 12390 15093 12392 2 (set (reg:SI 8731 [8730])
        (plus:SI (reg:SI 8731 [8730])
            (reg:SI 10838))) regex.i:8483 718 {*thumb1_addsi3}
     (expr_list:REG_DEAD (reg:SI 10838)
        (nil)))
regex.i:10121:1: internal compiler error: in assign_by_spills, at
lra-assigns.c:1419
0xa36eea _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
    ../../src/gcc/gcc/rtl-error.c:110
0x9521e7 assign_by_spills
    ../../src/gcc/gcc/lra-assigns.c:1419
0x952bd3 lra_assign()
    ../../src/gcc/gcc/lra-assigns.c:1594
0x94e919 lra(_IO_FILE*)
    ../../src/gcc/gcc/lra.c:2360
0x90cc09 do_reload
    ../../src/gcc/gcc/ira.c:5418
0x90cc09 execute
    ../../src/gcc/gcc/ira.c:5589
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <http://gcc.gnu.org/bugs.html> for instructions.

This issue still happens to the latest trunk.
>From gcc-bugs-return-483070-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Thu Apr 09 07:15:21 2015
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https://gcc.gnu.org/bugzilla/show_bug.cgi?ide684

Alexander Vogt <a.vogt at fulguritus dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
  Attachment #35263|0                           |1
        is obsolete|                            |

--- Comment #11 from Alexander Vogt <a.vogt at fulguritus dot com> ---
Created attachment 35269
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id5269&actioníit
Improved wording

[Bug target/65710] [5 Regression] Thumb1 ICE caused by no register to spill

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |arm-none-eabi
   Target Milestone|---                         |5.0

[Bug target/65710] [5 Regression] Thumb1 ICE caused by no register to spill

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
Needs confirming/reducing.

[Bug target/65710] [5 Regression] Thumb1 ICE caused by no register to spill

[terry.guo at arm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #2 from Terry Guo <terry.guo at arm dot com> ---
(In reply to Richard Biener from comment #1)
> Needs confirming/reducing.

Working on reducing.

[Bug target/65710] [5 Regression] Thumb1 ICE caused by no register to spill

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #3 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
Author: vmakarov
Date: Thu Apr  9 19:40:09 2015
New Revision: 221956

URL: https://gcc.gnu.org/viewcvs?rev=221956&root=gcc&view=rev
Log:
2015-04-09  Vladimir Makarov  <vmakarov@redhat.com>

    PR target/65710
    * lra-int.h (lra_bad_spill_regno_start): New.
    * lra.c (lra_bad_spill_regno_start): New.
    (lra): Set up lra_bad_spill_regno_start.  Set up
    lra_constraint_new_regno_start unconditionally.
    * lra-assigns.c (spill_for): Use lra_bad_spill_regno_start for
    spill preferences.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/lra-assigns.c
    trunk/gcc/lra-int.h
    trunk/gcc/lra.c

[Bug target/65710] [5 Regression] Thumb1 ICE caused by no register to spill

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #4 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
Author: vmakarov
Date: Thu Apr  9 19:42:24 2015
New Revision: 221957

URL: https://gcc.gnu.org/viewcvs?rev=221957&root=gcc&view=rev
Log:
2015-04-09  Vladimir Makarov  <vmakarov@redhat.com>

    PR target/65710
    * lra-int.h (lra_bad_spill_regno_start): New.
    * lra.c (lra_bad_spill_regno_start): New.
    (lra): Set up lra_bad_spill_regno_start.  Set up
    lra_constraint_new_regno_start unconditionally.
    * lra-assigns.c (spill_for): Use lra_bad_spill_regno_start for
    spill preferences.


Modified:
    branches/gcc-4_9-branch/gcc/ChangeLog
    branches/gcc-4_9-branch/gcc/lra-assigns.c
    branches/gcc-4_9-branch/gcc/lra-int.h
    branches/gcc-4_9-branch/gcc/lra.c

[Bug target/65710] [5 Regression] Thumb1 ICE caused by no register to spill

[terry.guo at arm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #6 from Terry Guo <terry.guo at arm dot com> ---
Created attachment 35285
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35285&action=edit
A late reduced test case

[Bug target/65710] [5 Regression] Thumb1 ICE caused by no register to spill

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
The testcase is ok for trunk with proper ChangeLog and if placed into
gcc.target/arm.

[Bug target/65710] [5 Regression] Thumb1 ICE caused by no register to spill

[evstupac at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

Stupachenko Evgeny <evstupac at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |evstupac at gmail dot com

--- Comment #8 from Stupachenko Evgeny <evstupac at gmail dot com> ---
The patch most likely (currently bisecting to get exact commit) caused 15%
regression on spec2000 164.gzip test compiled with "-Ofast -funroll-loops -flto
-march=slm -m32 -fPIE -pie".
(reproducible on Sandybridge).

[Bug target/65710] [4.9 Regression] Thumb1 ICE caused by no register to spill

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|5.0                         |4.9.3
            Summary|[5 Regression] Thumb1 ICE   |[4.9 Regression] Thumb1 ICE
                   |caused by no register to    |caused by no register to
                   |spill                       |spill

[Bug target/65710] [4.9 Regression] Thumb1 ICE caused by no register to spill

[yroux at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

Yvan Roux <yroux at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |yroux at gcc dot gnu.org
   Target Milestone|4.9.3                       |5.0

--- Comment #10 from Yvan Roux <yroux at gcc dot gnu.org> ---
LRA is also stuck in a loop when building gcc.target/arm/pr65647-2.c with
trunk.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|5.0                         |4.9.3
            Summary|[4.9 Regression] Thumb1 ICE |[4.9/5 Regression] Thumb1
                   |caused by no register to    |ICE caused by no register
                   |spill                       |to spill

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[evstupac at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #13 from Stupachenko Evgeny <evstupac at gmail dot com> ---
The issue reproduced with -march=corei7 as well.

Currently the hottest loop looks as following:
L1.
mov    (%esp),%ebp /* potentially redundant.  */
and    $0x7fff,%ebp                                          
movzwl 0x400(%esi,%ebp,2),%ecx                               
mov    %ecx,(%esp) 
cmp    %ecx,0x4(%esp) /*  Why not reuse ebp?  */        
jae    380                                                   
subl   $0x1,0x8(%esp)                                        
je     380                                                   
mov    (%esp),%ebp /* ebp could contain correct value (if reused above).  */
add    %edi,%ebp                                             
cmp    0x0(%ebp,%ebx,1),%al                                  
jne    L1
movzbl 0xf(%esp),%edx                                       
cmp    -0x1(%ebp,%ebx,1),%dl                               
jne    L1

Unnecessary fills and spills of ebp added.
Before the patch the loop was 2 instruction shorter.

L1.
and    $0x7fff,%edx                                             
movzwl 0x400(%esi,%edx,2),%edx                                  
cmp    %edx,0x4(%esp)                                           
jae    3c0                                                      
sub    $0x1,%ebp                                                
je     3c0                                                      
lea    (%edi,%edx,1),%ecx                                       
movzbl (%esp),%eax                                              
cmp    (%ecx,%ebx,1),%al                                        
jne    L1
movzbl 0xb(%esp),%eax                                           
cmp    -0x1(%ecx,%ebx,1),%al                                    
jne    L1.

Please let me know if you need dumps.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|P3                          |P1

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

Vladimir Makarov <vmakarov at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |vmakarov at gcc dot gnu.org

--- Comment #14 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Stupachenko Evgeny from comment #13)
> The issue reproduced with -march=corei7 as well.
> 
> Currently the hottest loop looks as following:
> L1.
> mov    (%esp),%ebp /* potentially redundant.  */
> and    $0x7fff,%ebp                                          
> movzwl 0x400(%esi,%ebp,2),%ecx                               
> mov    %ecx,(%esp) 
> cmp    %ecx,0x4(%esp) /*  Why not reuse ebp?  */        
> jae    380                                                   
> subl   $0x1,0x8(%esp)                                        
> je     380                                                   
> mov    (%esp),%ebp /* ebp could contain correct value (if reused above).  */
> add    %edi,%ebp                                             
> cmp    0x0(%ebp,%ebx,1),%al                                  
> jne    L1
> movzbl 0xf(%esp),%edx                                       
> cmp    -0x1(%ebp,%ebx,1),%dl                               
> jne    L1
> 
> Unnecessary fills and spills of ebp added.
> Before the patch the loop was 2 instruction shorter.
> 
> L1.
> and    $0x7fff,%edx                                             
> movzwl 0x400(%esi,%edx,2),%edx                                  
> cmp    %edx,0x4(%esp)                                           
> jae    3c0                                                      
> sub    $0x1,%ebp                                                
> je     3c0                                                      
> lea    (%edi,%edx,1),%ecx                                       
> movzbl (%esp),%eax                                              
> cmp    (%ecx,%ebx,1),%al                                        
> jne    L1
> movzbl 0xb(%esp),%eax                                           
> cmp    -0x1(%ecx,%ebx,1),%al                                    
> jne    L1.
> 
> Please let me know if you need dumps.

Could you add a pre-processed file with the hot loop.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #15 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
To be clear, I think we can postpone fixing the performance issue till 5.2/6.
The reason this is a P1 is #c9, #c10, #c11.  Vlad, can you please have a look
at that?

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[evstupac at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #16 from Stupachenko Evgeny <evstupac at gmail dot com> ---
I can't attach spec2000 benchmarks sources.
The loop is in "longest_match" function in 164.gzip.

Options to reproduce: "-Ofast -funroll-loops -flto -march=corei7 -m32 -fPIE
-pie" (-march=slm reproduce the issue as well).

I'm checking if the issue reproduced without "-flto".

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #17 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Stupachenko Evgeny from comment #16)
> I can't attach spec2000 benchmarks sources.
> The loop is in "longest_match" function in 164.gzip.
> 
> Options to reproduce: "-Ofast -funroll-loops -flto -march=corei7 -m32 -fPIE
> -pie" (-march=slm reproduce the issue as well).
> 
> I'm checking if the issue reproduced without "-flto".

But gzip is free software, so just attach preprocessed source of some free
version from around the same time after checking it generates the same code for
the loop?

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #18 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Jakub Jelinek from comment #15)
> To be clear, I think we can postpone fixing the performance issue till 5.2/6.
> The reason this is a P1 is #c9, #c10, #c11.  Vlad, can you please have a
> look at that?

Ok.  I'll be working on it for gcc-4.9.

Thanks for the clarification.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #19 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Vladimir Makarov from comment #18)
> (In reply to Jakub Jelinek from comment #15)
> > To be clear, I think we can postpone fixing the performance issue till 5.2/6.
> > The reason this is a P1 is #c9, #c10, #c11.  Vlad, can you please have a
> > look at that?
> 
> Ok.  I'll be working on it for gcc-4.9.
> 
> Thanks for the clarification.

#c10 says it happens on the trunk too.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[evstupac at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #20 from Stupachenko Evgeny <evstupac at gmail dot com> ---
(In reply to Stupachenko Evgeny from comment #16)

> I'm checking if the issue reproduced without "-flto".

Unfortunately, "-flto" required to reproduce the issue.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #22 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Yvan Roux from comment #21)
> (In reply to Jakub Jelinek from comment #19)
> > (In reply to Vladimir Makarov from comment #18)
> > > (In reply to Jakub Jelinek from comment #15)
> > > > To be clear, I think we can postpone fixing the performance issue till 5.2/6.
> > > > The reason this is a P1 is #c9, #c10, #c11.  Vlad, can you please have a
> > > > look at that?
> > > 
> > > Ok.  I'll be working on it for gcc-4.9.
> > > 
> > > Thanks for the clarification.
> > 
> > #c10 says it happens on the trunk too.
> 
> I can't check full validation results right now, but the suggested fix in
> #c11 seems to fix the issue

Why is pr65648-2.c testcase missing from the trunk?  I see it only on the 4.9
branch...

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[yroux at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #23 from Yvan Roux <yroux at gcc dot gnu.org> ---

(In reply to Jakub Jelinek from comment #22)

> Why is pr65648-2.c testcase missing from the trunk?  I see it only on the
> 4.9 branch...

Yes my fault, I was dealing with this 4.9 regression when PR65648 was fixed on
trunk, so I proposed the backporting fix for 4.9 branch with the testcase
pr65648-2.c which was failing on 4.9 and not on trunk.  I should have committed
it on trunk as well.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #24 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Yvan Roux from comment #23)
> I should have committed it on trunk as well.

Please do so now, thanks.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #25 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
Author: vmakarov
Date: Fri Apr 10 19:38:55 2015
New Revision: 221983

URL: https://gcc.gnu.org/viewcvs?rev=221983&root=gcc&view=rev
Log:
2015-04-10  Vladimir Makarov  <vmakarov@redhat.com>

    PR target/65710
    * lra-assigns.c (spill_for): Update smallest_bad_spills_num.
    Print bad_spills_num and insn_pseudos_num.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/lra-assigns.c

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #26 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
Author: vmakarov
Date: Fri Apr 10 19:43:28 2015
New Revision: 221984

URL: https://gcc.gnu.org/viewcvs?rev=221984&root=gcc&view=rev
Log:
2015-04-10  Vladimir Makarov  <vmakarov@redhat.com>

    PR target/65710
    * lra-assigns.c (spill_for): Update smallest_bad_spills_num.
    Print bad_spills_num and insn_pseudos_num.


Modified:
    branches/gcc-4_9-branch/gcc/ChangeLog
    branches/gcc-4_9-branch/gcc/lra-assigns.c

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #27 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Stupachenko Evgeny from comment #16)
> I can't attach spec2000 benchmarks sources.
> The loop is in "longest_match" function in 164.gzip.
> 
> Options to reproduce: "-Ofast -funroll-loops -flto -march=corei7 -m32 -fPIE
> -pie" (-march=slm reproduce the issue as well).
> 
> I'm checking if the issue reproduced without "-flto".

Evgeny, could you check the effect of my latest patch (c25) on gzip.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[yroux at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #28 from Yvan Roux <yroux at gcc dot gnu.org> ---
(In reply to Vladimir Makarov from comment #25)
> Author: vmakarov
> Date: Fri Apr 10 19:38:55 2015
> New Revision: 221983
> 
> URL: https://gcc.gnu.org/viewcvs?rev=221983&root=gcc&view=rev
> Log:
> 2015-04-10  Vladimir Makarov  <vmakarov@redhat.com>
> 
> 	PR target/65710
> 	* lra-assigns.c (spill_for): Update smallest_bad_spills_num.
> 	Print bad_spills_num and insn_pseudos_num.

That indeed makes more sense than my workaround, I'm progressing in LRA but
there is still way to go ! ;) Thanks Vlad
>From gcc-bugs-return-483352-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Fri Apr 10 20:49:57 2015
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From: "evstupac at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill
Date: Fri, 10 Apr 2015 20:49:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?ide710

--- Comment #29 from Stupachenko Evgeny <evstupac at gmail dot com> ---
>Evgeny, could you check the effect of my latest patch (c25) on gzip.

The performance is back. Thanks.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|REOPENED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #30 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
So hopefully fixed now.

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[xguo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #31 from xuepeng guo <xguo at gcc dot gnu.org> ---
Author: xguo
Date: Mon Apr 13 05:22:09 2015
New Revision: 222037

URL: https://gcc.gnu.org/viewcvs?rev=222037&root=gcc&view=rev
Log:
Add missing test case

2015-04-13  Terry Guo  <terry.guo@arm.com>

        PR target/65710
        * gcc.target/arm/pr65710.c: New.

Added:
    trunk/gcc/testsuite/gcc.target/arm/pr65710.c
Modified:
    trunk/gcc/testsuite/ChangeLog

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #32 from clyon at gcc dot gnu.org ---

> 2015-04-13  Terry Guo  <terry.guo@arm.com>
> 
>         PR target/65710
>         * gcc.target/arm/pr65710.c: New.
> 

Terry, any particular reason you use -march=armv6-m instead of -march=armv6 ?

Some of my test configurations add -marm to RUNTESTFLAGS, and they fail
because:
error: target CPU does not support ARM mode

Can we switch to armv6, or do we need a few additional guards to avoid running
this test in unsupported configurations?

[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill

[terry.guo at arm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710

--- Comment #33 from Terry Guo <terry.guo at arm dot com> ---
(In reply to clyon from comment #32)
> > 2015-04-13  Terry Guo  <terry.guo@arm.com>
> > 
> >         PR target/65710
> >         * gcc.target/arm/pr65710.c: New.
> > 
> 
> Terry, any particular reason you use -march=armv6-m instead of -march=armv6 ?
> 
> Some of my test configurations add -marm to RUNTESTFLAGS, and they fail
> because:
> error: target CPU does not support ARM mode
> 
> Can we switch to armv6, or do we need a few additional guards to avoid
> running this test in unsupported configurations?

Thanks for reminding. I just made a stupid copy-paste error here. The correct
options should be "-mthumb -O2 -mfloat-abi=soft" as shown in comment#1. I
reused some test case template and forgot to update the options. I will fix
this soon.