[Bug target/65730] New: xtensa: ICE in libstdc++-v3/include/bits/atomic_base.h: In function ‘bool std::atomic_flag_test_and_set_explicit(std::__atomic_flag_base*, std::memory_order)’

[Bug target/65730] New: xtensa: ICE in libstdc++-v3/include/bits/atomic_base.h: In function ‘bool std::atomic_flag_test_and_set_explicit(std::__atomic_flag_base*, std::memory_order)’

[jcmvbkbc at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65730

            Bug ID: 65730
           Summary: xtensa: ICE in
                    libstdc++-v3/include/bits/atomic_base.h: In function
                    ‘bool
                    std::atomic_flag_test_and_set_explicit(std::__atomic_f
                    lag_base*, std::memory_order)’
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jcmvbkbc at gcc dot gnu.org

Created attachment 35287
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35287&action=edit
preprocessed source

With overlay that has no hardware multiplication option building libstdc++ ends
with ICE:

cc1plus -std=gnu++11 compatibility-atomic-c++0x.ii

In file included from
/home/jcmvbkbc/tmp/jr/Max_Fusion_MMU_KC705/build-buildroot/build/host-gcc-final-4.8.4/build/xtensa-buildroot-linux-uclibc/libstdc++-v3/include/atomic:41:0,
                 from
../../../../libstdc++-v3/src/c++11/compatibility-atomic-c++0x.cc:26:
/home/jcmvbkbc/tmp/jr/Max_Fusion_MMU_KC705/build-buildroot/build/host-gcc-final-4.8.4/build/xtensa-buildroot-linux-uclibc/libstdc++-v3/include/bits/atomic_base.h:
In member function ‘bool std::atomic_flag::test_and_set(std::memory_order)’:
/home/jcmvbkbc/tmp/jr/Max_Fusion_MMU_KC705/build-buildroot/build/host-gcc-final-4.8.4/build/xtensa-buildroot-linux-uclibc/libstdc++-v3/include/bits/atomic_base.h:287:47:
internal compiler error: Segmentation fault
       return __atomic_test_and_set (&_M_i, __m);
                                               ^
0xed8ae7 crash_signal
        ../../gcc/gcc/toplev.c:383
0xdba4e1 widened_mode
        ../../gcc/gcc/optabs.c:303
0xdbd699 expand_binop(machine_mode, optab_tag, rtx_def*, rtx_def*, rtx_def*,
int, optab_methods)
        ../../gcc/gcc/optabs.c:1561
0xdbce5a expand_simple_binop(machine_mode, rtx_code, rtx_def*, rtx_def*,
rtx_def*, int, optab_methods)
        ../../gcc/gcc/optabs.c:1313
0x1248be4 init_alignment_context
        ../../gcc/gcc/config/xtensa/xtensa.c:1470
0x1248cb4 xtensa_expand_compare_and_swap(rtx_def*, rtx_def*, rtx_def*,
rtx_def*)
        ../../gcc/gcc/config/xtensa/xtensa.c:1494
0x125383e gen_sync_compare_and_swapqi(rtx_def*, rtx_def*, rtx_def*, rtx_def*)
        ../../gcc/gcc/config/xtensa/xtensa.md:1977
0xdcee66 insn_gen_fn::operator()(rtx_def*, rtx_def*, rtx_def*, rtx_def*) const
        ../../gcc/gcc/recog.h:305
0xdcddc5 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
        ../../gcc/gcc/optabs.c:8391
0xdce0c2 maybe_expand_insn(insn_code, unsigned int, expand_operand*)
        ../../gcc/gcc/optabs.c:8421
0xdcc1c1 expand_atomic_compare_and_swap(rtx_def**, rtx_def**, rtx_def*,
rtx_def*, rtx_def*, bool, memmodel, memmodel)
        ../../gcc/gcc/optabs.c:7533
0xdcb856 expand_compare_and_swap_loop
        ../../gcc/gcc/optabs.c:7182
0xdcbba7 maybe_emit_compare_and_swap_exchange_loop
        ../../gcc/gcc/optabs.c:7294
0xdcbd6d expand_atomic_test_and_set(rtx_def*, rtx_def*, memmodel)
        ../../gcc/gcc/optabs.c:7406
0x98afc6 expand_builtin_atomic_test_and_set
        ../../gcc/gcc/builtins.c:5679
0x98e5a1 expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int)
        ../../gcc/gcc/builtins.c:6974
0xb0b404 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
        ../../gcc/gcc/expr.c:10488
0xb00e4a expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_modifier,
rtx_def**, bool)
        ../../gcc/gcc/expr.c:8017
0xae8ff3 expand_expr
        ../../gcc/gcc/expr.h:254
0xaf6f2f store_expr_with_bounds(tree_node*, rtx_def*, int, bool, tree_node*)
        ../../gcc/gcc/expr.c:5290

This is reproducible with current mainline and with 4.9.4.
>From gcc-bugs-return-483299-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Fri Apr 10 13:16:58 2015
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From: "yroux at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill
Date: Fri, 10 Apr 2015 13:16:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?ide710

--- Comment #11 from Yvan Roux <yroux at gcc dot gnu.org> ---
Re-introducing the condition that stop updating lra_constraint_new_regno_start
after switching off inheritance and remat, seems to fix the problem:
gcc.target/arm/pr65647-2.c is ok and the reduced test case from Terry builds as
well, at least with my quick test on 4.9 branch.  I'll do it on trunk and pass
a full validation.

Is it the correct fix for you Vlad ?

[Bug target/65730] xtensa: ICE in libstdc++-v3/include/bits/atomic_base.h: In function ‘bool std::atomic_flag_test_and_set_explicit(std::__atomic_flag_base*, std::memory_order)’

[jcmvbkbc at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65730

jcmvbkbc at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2015-04-10
           Assignee|unassigned at gcc dot gnu.org      |jcmvbkbc at gcc dot gnu.org
     Ever confirmed|0                           |1

--- Comment #1 from jcmvbkbc at gcc dot gnu.org ---
Created attachment 35288
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35288&action=edit
xtensa configuration overlay

[Bug target/65730] xtensa: ICE in libstdc++-v3/include/bits/atomic_base.h: In function ‘bool std::atomic_flag_test_and_set_explicit(std::__atomic_flag_base*, std::memory_order)’

[jcmvbkbc at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65730

--- Comment #2 from jcmvbkbc at gcc dot gnu.org ---
Author: jcmvbkbc
Date: Wed May 20 18:56:14 2015
New Revision: 223452

URL: https://gcc.gnu.org/viewcvs?rev=223452&root=gcc&view=rev
Log:
Fix PR target/65730

2015-05-20  Max Filippov  <jcmvbkbc@gmail.com>
gcc/
        * config/xtensa/xtensa.c (init_alignment_context): Replace MULT
        by BITS_PER_UNIT with ASHIFT by exact_log2 (BITS_PER_UNIT).


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/xtensa/xtensa.c

[Bug target/65730] xtensa: ICE in libstdc++-v3/include/bits/atomic_base.h: In function ‘bool std::atomic_flag_test_and_set_explicit(std::__atomic_flag_base*, std::memory_order)’

[jcmvbkbc at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65730

jcmvbkbc at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #3 from jcmvbkbc at gcc dot gnu.org ---
Fixed.