[Bug rtl-optimization/65862] [MIPS] IRA/LRA issue: integers spilled to floating-point registers

["wdijkstr at arm dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65862

--- Comment #4 from Wilco <wdijkstr at arm dot com> ---
(In reply to Vladimir Makarov from comment #3)

But I can not just revert the patch making ALL_REGS available
> to make
coloring heuristic more fotunate for your particular case, as it
> reopens the old PR for which the patch was created and i have no other
> solutions for the old PR.

I tried reverting the ALL_REGS patch and I don't see any regressions - in fact
allocations are slightly better (fewer registers with ALL_REGS preference which
is what we need - a strong decision to allocate to either FP or int regs). So
what was the motivation for it?

Note that it would be trivial to prefer ALL_REGS for some operands if
necessary. The only case I can imagine is load and store which on some targets
are quite orthogonal. I tried doing m=r#w and m=w#r on AArch64 and that works
fine (this tells the preferencing code that ALL_REGS is best but it still keeps
a clear INT/FP separation in the patterns which you may need for disassembly
etc).

IMHO that is a better solution than to automatically change the patterns r=r+r;
w=w+w into rw=rw+rw and assume that ALL_REGS preference on all operands has
zero cost eventhough the cost calculation explicitly states otherwise.