From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29715 invoked by alias); 14 May 2015 14:20:56 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 29663 invoked by uid 48); 14 May 2015 14:20:50 -0000 From: "wdijkstr at arm dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/65862] [MIPS] IRA/LRA issue: integers spilled to floating-point registers Date: Thu, 14 May 2015 14:20:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 5.1.1 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: wdijkstr at arm dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-05/txt/msg01124.txt.bz2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65862 --- Comment #13 from Wilco --- (In reply to Vladimir Makarov from comment #9) > Created attachment 35503 [details] > ira-hook.patch > > Here is the patch. Could you try it and give me your opinion about it. > Thanks. I tried it out and when forcing ALL_REGS to either GENERAL_REGS or FP_REGS based on mode it generates significantly smaller spillcode, especially on some of the high register pressure SPECFP2006 benchmarks like gamess. It is better than avoiding ALL_REGS if the cost is higher (like the PPC patch mentioned earlier) - this indicates that the case for preferring ALL_REGS for generic loads/stores is pretty thin and likely not beneficial overall. I'm glad with this we're moving towards a more conventional allocation scheme where the decision of which register class to use is made early rather than independently for each operand during allocation. I didn't do a full performance regression test but early results show identical performance with smaller codesize. Note that this doesn't solve the lra-constraints issue where it ignores the allocno class during spilling and just chooses the first variant that matches.