[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[ubizjak at gmail dot com]

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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ubizjak at gmail dot com

--- Comment #2 from Uroš Bizjak <ubizjak at gmail dot com> ---
Created attachment 35411
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35411&action=edit
Prototype patch for bextr and bzhi

Prototype patch that removes flag checks for bextr and bzhi insns.
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From: "nikolay.pakulin at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug c/65916] New: Unnecessary floating-point instruction causes runtime exception on PowerPC
Date: Tue, 28 Apr 2015 13:06:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?ide916

            Bug ID: 65916
           Summary: Unnecessary floating-point instruction causes runtime
                    exception on PowerPC
           Product: gcc
           Version: 4.9.1
            Status: UNCONFIRMED
          Severity: critical
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: nikolay.pakulin at gmail dot com
  Target Milestone: ---

Created attachment 35412
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id5412&actioníit
Test case to reproduce the issue

Writing 64-bit integers to memory on 32-bit PPC involves floating point
register FP0.  When floating-point support is disabled (bit FP is cleared in
MSR register) the generated code leads to exception "FP unavailable interrupt".

The test case compiled by GCC cross compiler running on x86_64 Linux.

powerpc-elf-gcc -S -m32 -mcpuå00mc uint64.c


-- uint64.c --
typedef unsigned long long u64;

u64 globvar;

void f(u64 arg) {
  globvar = arg;
}
-- /uint64.c --

-- Generated ASM --
f:
        stwu 1,-32(1)
        stw 31,28(1)
        mr 31,1
        stw 3,8(31)     # Copies 'arg' to the temporary on the stack
        stw 4,12(31)    #
        lis 9,globvar@ha
        la 9,globvar@l(9)
        lfd 0,8(31)     # Loads the temporary to FP0 -- exception!
        stfd 0,0(9)     # Store FP0 to memory
        addi 11,31,32
        lwz 31,-4(11)
        mr 1,11
        blr
-- End of Generated ASM --

== GCC specs =Using built-in specs.
COLLECT_GCC=powerpc-elf-gcc
COLLECT_LTO_WRAPPER=/opt/crosstools/powerpc-elf-4.9.1-Linux-x86_64/bin/../libexec/gcc/powerpc-elf/4.9.1/lto-wrapper
Target: powerpc-elf
Configured with: ../gcc-4.9.1/configure --target=powerpc-elf
--prefix=/home/geist/svn/toolchains/powerpc-elf-4.9.1-Linux-x86_64
--enable-languages=c,c++ --disable-werror
Thread model: single
gcc version 4.9.1 (GCC)
== End of GCC specs =
The workaround is to compile with optimization turned on. With -O switch GCC
produces ASM without FP0:

powerpc-elf-gcc -S -m32 -mcpuå00mc -O uint64.c
-- Generated optimized ASM --
f:
        lis 9,globvar@ha
        la 9,globvar@l(9)
        stw 3,0(9)        # direct write to the destination
        stw 4,4(9)        #
        blr
-- End of generated optimized ASM --

[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2015-04-28
     Ever confirmed|0                           |1

--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to James Almer from comment #1)
> The same apparently happens with bextr, blsi, blsr, and most (if not all) of
> AMD's tbm instructions. They set the ZF flag but gcc still generates a test
> instruction.

Please see the patch, attached in Comment #2.

While I can see the use (and benefit) to model the patterns that also set CC
register internally for BEXTR and BZHI instructions, I don't think other listed
instructions have clear usage scenarios to warrant additional patterns.

Can you perhaps show the benefit to have more insns modelled this way?
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https://gcc.gnu.org/bugzilla/show_bug.cgi?ida645

Jonathan Wakely <redi at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #7 from Jonathan Wakely <redi at gcc dot gnu.org> ---
done

[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[jamrial at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

--- Comment #4 from James Almer <jamrial at gmail dot com> ---
(In reply to Uroš Bizjak from comment #3)
> Please see the patch, attached in Comment #2.
> 
> While I can see the use (and benefit) to model the patterns that also set CC
> register internally for BEXTR and BZHI instructions, I don't think other
> listed instructions have clear usage scenarios to warrant additional
> patterns.
> 
> Can you perhaps show the benefit to have more insns modelled this way?

Not really, i simply assumed that taking into consideration what flags these
instructions affected in every case was the intended behavior, so figured it
was worth pointing them out.
I'm mainly interested in bzhi (and by extension bextr).
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Subject: [Bug bootstrap/65910] r222473 breaks x86_64 darwin bootstrap
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https://gcc.gnu.org/bugzilla/show_bug.cgi?ide910

--- Comment #4 from Caroline Tice <cmtice at google dot com> ---
Has anyone actually committed this fix?  I'm not seeing it in my tree yet....

[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[uros at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

--- Comment #5 from uros at gcc dot gnu.org ---
Author: uros
Date: Wed Apr 29 18:53:19 2015
New Revision: 222588

URL: https://gcc.gnu.org/viewcvs?rev=222588&root=gcc&view=rev
Log:
        PR target/65871
        * config/i386/i386.md (*bmi_bextr_<mode>_cczonly): New pattern.
        (*bmi2_bzhi_<mode>3_1_cczonly): Ditto.

testsuite/ChangeLog:

        PR target/65871
        * gcc.target/i386/pr65871-1.c: New test
        * gcc.target/i386/pr65871-2.c: Ditto.


Added:
    trunk/gcc/testsuite/gcc.target/i386/pr65871-1.c
    trunk/gcc/testsuite/gcc.target/i386/pr65871-2.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.md
    trunk/gcc/testsuite/ChangeLog

[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[uros at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

--- Comment #6 from uros at gcc dot gnu.org ---
Author: uros
Date: Wed Apr 29 20:58:25 2015
New Revision: 222592

URL: https://gcc.gnu.org/viewcvs?rev=222592&root=gcc&view=rev
Log:
        PR target/65871
        * config/i386/i386.md (*bmi_bextr_<mode>_cczonly): New pattern.
        (*bmi2_bzhi_<mode>3_1_cczonly): Ditto.
        (setcc+movzbl peephole2): Check also clobbered reg.
        (setcc+andl peephole2): Ditto.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.md

[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[jamrial at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

--- Comment #7 from James Almer <jamrial at gmail dot com> ---
Thanks for the above fix.

I forgot to test BMI1's andn. That one should have an insn modeled this way as
well.

int foo (unsigned int x, unsigned int y)
{
    if (~x & y)
        return 1;
    return 0;
}


gcc -O2 -mbmi -c andn.c

0000000000000000 <foo>:
   0:   c4 e2 40 f2 fe          andn   %esi,%edi,%edi
   5:   31 c0                   xor    %eax,%eax
   7:   85 ff                   test   %edi,%edi
   9:   0f 95 c0                setne  %al
   c:   c3                      retq

http://www.felixcloutier.com/x86/ANDN.html

[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[uros at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

--- Comment #8 from uros at gcc dot gnu.org ---
Author: uros
Date: Tue May  5 04:36:19 2015
New Revision: 222795

URL: https://gcc.gnu.org/viewcvs?rev=222795&root=gcc&view=rev
Log:
        PR target/65871
        * config/i386/i386.md (*bmi_andn_<mode>_ccno): New pattern.

testsuite/ChangeLog:

        PR target/65871
        * gcc.target/i386/pr65871-3.c: New test.


Added:
    trunk/gcc/testsuite/gcc.target/i386/pr65871-3.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.md
    trunk/gcc/testsuite/ChangeLog

[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[jamrial at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

--- Comment #9 from James Almer <jamrial at gmail dot com> ---
Created attachment 35804
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35804&action=edit
Preprocessed code where a test instruction is still generated

Please look at the attachment.

[jamrial@archVM ~]$ gcc -std=c99 -march=haswell -O3 -c hevc_ps.i

[jamrial@archVM ~]$ objdump --disassemble hevc_ps.o | grep -B2 -A2 bzhi
    5854:       c4 62 22 f7 d6          sarx   %r11d,%esi,%r10d
    5859:       c4 62 22 f7 da          sarx   %r11d,%edx,%r11d
    585e:       c4 e2 70 f5 f6          bzhi   %ecx,%esi,%esi
    5863:       45 89 9e 68 33 00 00    mov    %r11d,0x3368(%r14)
    586a:       41 89 c3                mov    %eax,%r11d
--
    589d:       85 f6                   test   %esi,%esi
    589f:       75 0d                   jne    58ae
<ff_hevc_decode_nal_sps+0x1a6e>
    58a1:       c4 e2 70 f5 d2          bzhi   %ecx,%edx,%edx
    58a6:       85 d2                   test   %edx,%edx
    58a8:       0f 84 5a 03 00 00       je     5c08
<ff_hevc_decode_nal_sps+0x1dc8>

[jamrial@archVM ~]$ gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/local/lib/gcc/x86_64-unknown-linux-gnu/6.0.0/lto-wrapper
Target: x86_64-unknown-linux-gnu
Configured with: /home/jamrial/gcc-svn/configure --prefix=/usr/local
--libdir=/usr/local/lib --libexecdir=/usr/local/lib
--mandir=/usr/local/share/man --infodir=/usr/local/share/info
--enable-languages=c,c++,lto --enable-shared --disable-bootstrap
--enable-threads=posix --enable-libmpx --with-system-zlib --enable-__cxa_atexit
--disable-libunwind-exceptions --enable-clocale=gnu --disable-libstdcxx-pch
--disable-libssp --enable-gnu-unique-object --enable-linker-build-id
--enable-lto --enable-plugin --enable-install-libiberty
--with-linker-hash-style=gnu --enable-gnu-indirect-function --disable-multilib
--disable-werror
Thread model: posix
gcc version 6.0.0 20150618 (experimental) (GCC)


Not sure why the new model is not working here.

[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

--- Comment #10 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to James Almer from comment #9)
> Created attachment 35804 [details]
> Preprocessed code where a test instruction is still generated
> 
> Please look at the attachment.
> 
> [jamrial@archVM ~]$ gcc -std=c99 -march=haswell -O3 -c hevc_ps.i
> 
> [jamrial@archVM ~]$ objdump --disassemble hevc_ps.o | grep -B2 -A2 bzhi
>     5854:       c4 62 22 f7 d6          sarx   %r11d,%esi,%r10d
>     5859:       c4 62 22 f7 da          sarx   %r11d,%edx,%r11d
>     585e:       c4 e2 70 f5 f6          bzhi   %ecx,%esi,%esi
>     5863:       45 89 9e 68 33 00 00    mov    %r11d,0x3368(%r14)
>     586a:       41 89 c3                mov    %eax,%r11d
> --
>     589d:       85 f6                   test   %esi,%esi
>     589f:       75 0d                   jne    58ae
> <ff_hevc_decode_nal_sps+0x1a6e>
>     58a1:       c4 e2 70 f5 d2          bzhi   %ecx,%edx,%edx
>     58a6:       85 d2                   test   %edx,%edx
>     58a8:       0f 84 5a 03 00 00       je     5c08
> <ff_hevc_decode_nal_sps+0x1dc8>

[...]

> Not sure why the new model is not working here.

Because of the cost model. Combine pass says:

Trying 2631 -> 2633:
Successfully matched this instruction:
(set (reg:CCZ 17 flags)
    (compare:CCZ (zero_extract:SI (reg:SI 2360 [ D.14992 ])
            (umin:SI (zero_extend:SI (subreg:QI (reg:SI 301 [ D.14999 ]) 0))
                (const_int 32 [0x20]))
            (const_int 0 [0]))
        (const_int 0 [0])))
rejecting combination of insns 2631 and 2633
original costs 12 + 4 = 16
replacement cost 18
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

--- Comment #11 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Uroš Bizjak from comment #10)

> Because of the cost model. Combine pass says:

Testing the patch:

--cut here--
Index: i386.c
===================================================================
--- i386.c      (revision 224630)
+++ i386.c      (working copy)
@@ -42533,6 +42533,12 @@ ix86_rtx_costs (rtx x, int code_i, int outer_code_
                    + rtx_cost (const1_rtx, outer_code, opno, speed));
          return true;
        }
+
+      /* The embedded comparison operand is completely free.  */
+      if (!general_operand (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
+         && XEXP (x, 1) == const0_rtx)
+       *total = 0;
+
       return false;

     case FLOAT_EXTEND:
--cut here--
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From: "michael.lehn@uni-ulm.de" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug c/66613] error in evaluationg cexp
Date: Sun, 21 Jun 2015 11:37:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idf613

Michael Lehn <michael.lehn@uni-ulm.de> changed:

           What    |Removed                     |Added
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                 CC|                            |michael.lehn@uni-ulm.de

--- Comment #1 from Michael Lehn <michael.lehn@uni-ulm.de> ---
> //> Terminated with exit code 0.

So were is the error?

[Bug target/65871] bzhi builtin/intrinsic wrongly assumes bzhi instruction doesn't set the ZF flag

[uros at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65871

--- Comment #12 from uros at gcc dot gnu.org ---
Author: uros
Date: Mon Jun 22 13:54:58 2015
New Revision: 224729

URL: https://gcc.gnu.org/viewcvs?rev=224729&root=gcc&view=rev
Log:
        PR target/65871
        * config/i386/i386.c (ix86_rtx_costs) <case COMPARE>: Ignore the
        cost of embedded comparison.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.c