From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 98300 invoked by alias); 7 May 2015 12:35:13 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 98212 invoked by uid 48); 7 May 2015 12:35:10 -0000 From: "vekumar at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/66049] New: Few AArch64 extend and add with shift tests generates sub optimal code with trunk gcc 6.0. Date: Thu, 07 May 2015 12:35:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 6.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: vekumar at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-05/txt/msg00576.txt.bz2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66049 Bug ID: 66049 Summary: Few AArch64 extend and add with shift tests generates sub optimal code with trunk gcc 6.0. Product: gcc Version: 6.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: vekumar at gcc dot gnu.org Target Milestone: --- After preventing conversion of shift to mults in combiner https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=222874 few Aarch64 target tests generates suboptimal code. Tests that now fail, but worked before: --------------------------------------- gcc.target/aarch64/adds1.c scan-assembler adds\tw[0-9]+, w[0-9]+, w[0-9]+, lsl 3 gcc.target/aarch64/adds1.c scan-assembler adds\tx[0-9]+, x[0-9]+, x[0-9]+, lsl 3 gcc.target/aarch64/adds3.c scan-assembler-times adds\tx[0-9]+, x[0-9]+, x[0-9]+, sxtw 2 gcc.target/aarch64/extend.c scan-assembler add\tw[0-9]+,.*uxth #?1 gcc.target/aarch64/extend.c scan-assembler add\tx[0-9]+,.*uxtw #?3 gcc.target/aarch64/extend.c scan-assembler sub\tw[0-9]+,.*uxth #?1 gcc.target/aarch64/extend.c scan-assembler sub\tx[0-9]+,.*uxth #?1 gcc.target/aarch64/extend.c scan-assembler sub\tx[0-9]+,.*uxtw #?3 gcc.target/aarch64/subs1.c scan-assembler subs\tw[0-9]+, w[0-9]+, w[0-9]+, lsl 3 gcc.target/aarch64/subs1.c scan-assembler subs\tx[0-9]+, x[0-9]+, x[0-9]+, lsl 3 gcc.target/aarch64/subs3.c scan-assembler-times subs\tx[0-9]+, x[0-9]+, x[0-9]+, sxtw 2 Sample Test case ---------------- unsigned long long adddi_uxtw (unsigned long long a, unsigned int i) { /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*uxtw #?3" } } */ return a + ((unsigned long long)i << 3); } Before add x0, x0, x1, uxtw 3 Now ubfiz x1, x1, 3, 32 add x0, x1, x0