[Bug target/66200] New: GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[Bug target/66200] New: GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[ramana at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

            Bug ID: 66200
           Summary: GCC for ARM / AArch64 doesn't define
                    TARGET_RELAXED_ORDERING
           Product: gcc
           Version: 4.8.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ramana at gcc dot gnu.org
  Target Milestone: ---

ARM / AArch64 have a relaxed memory model, the ports need to define
TARGET_RELAXED_ORDERING and the corresponding macros for libstdc++.

This has been a problem on the ARM port since the time the feature was
introduced into the compiler in 2004 and in the AArch64 port since the dawn of
time.

[Bug target/66200] GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[ramana at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

Ramana Radhakrishnan <ramana at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2015-05-19
           Assignee|unassigned at gcc dot gnu.org      |ramana at gcc dot gnu.org
     Ever confirmed|0                           |1
      Known to fail|                            |4.8.0, 4.8.1, 4.8.2, 4.8.3,
                   |                            |4.9.0, 4.9.1, 4.9.2, 5.0,
                   |                            |6.0

--- Comment #1 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
Working on this.

[Bug target/66200] GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[ramana at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

--- Comment #2 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
Author: ramana
Date: Thu Jun  4 09:19:51 2015
New Revision: 224118

URL: https://gcc.gnu.org/viewcvs?rev=224118&root=gcc&view=rev
Log:
Remove TARGET_RELAXED_ORDERING and optimize for weak memory models.


This patch removes the special casing for targets with relaxed
memory ordering and handles guard accesses with equivalent
atomic load acquire operations. In this process we change the
algorithm to load the guard variable with an atomic load that
has ACQUIRE semantics.

This then means that on targets which have weak memory models, the
fast path is inlined and can directly use a load-acquire instruction
where available (and yay! one more hook gone).

2015-06-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR c++/66192
        PR target/66200
        * doc/tm.texi: Regenerate.
        * doc/tm.texi.in (TARGET_RELAXED_ORDERING): Delete.
        * target.def (TARGET_RELAXED_ORDERING): Likewise.
        * config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Likewise.
        * config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Likewise.
        * config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Likewise.
        * config/sparc/linux.h (SPARC_RELAXED_ORDERING): Likewise.
        * config/sparc/linux64.h (SPARC_RELAXED_ORDERING): Likewise.
        * config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Likewise.
        * config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Likewise.
        * system.h (TARGET_RELAXED_ORDERING): Poison.

2015-06-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR c++/66192
        PR target/66200
        * cp-tree.h (get_guard_cond): Adjust declaration
        * decl.c (expand_static_init): Use atomic load acquire
        and adjust call to get_guard_cond.
        * decl2.c (build_atomic_load_byte): New function.
        (get_guard_cond): Handle thread_safety.
        (one_static_initialization_or_destruction): Adjust call to
        get_guard_cond.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/alpha/alpha.c
    trunk/gcc/config/ia64/ia64.c
    trunk/gcc/config/rs6000/rs6000.c
    trunk/gcc/config/sparc/linux.h
    trunk/gcc/config/sparc/linux64.h
    trunk/gcc/config/sparc/sparc.c
    trunk/gcc/config/sparc/sparc.h
    trunk/gcc/cp/ChangeLog
    trunk/gcc/cp/cp-tree.h
    trunk/gcc/cp/decl.c
    trunk/gcc/cp/decl2.c
    trunk/gcc/doc/tm.texi
    trunk/gcc/doc/tm.texi.in
    trunk/gcc/system.h
    trunk/gcc/target.def

[Bug target/66200] GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[ramana at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

--- Comment #3 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
Fixed on trunk so far.

[Bug target/66200] GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[singhai at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

--- Comment #4 from Sharad Singhai <singhai at gcc dot gnu.org> ---
Author: singhai
Date: Tue Jun  9 06:45:43 2015
New Revision: 224265

URL: https://gcc.gnu.org/viewcvs?rev=224265&root=gcc&view=rev
Log:
Backport r224118 from trunk for Google ref b/20542176 and b/20766120.

Remove TARGET_RELAXED_ORDERING and optimize for weak memory models.


This patch removes the special casing for targets with relaxed
memory ordering and handles guard accesses with equivalent
atomic load acquire operations. In this process we change the
algorithm to load the guard variable with an atomic load that
has ACQUIRE semantics.

This then means that on targets which have weak memory models, the
fast path is inlined and can directly use a load-acquire instruction
where available (and yay! one more hook gone).

2015-06-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

            PR c++/66192
            PR target/66200
            * doc/tm.texi: Regenerate.
            * doc/tm.texi.in (TARGET_RELAXED_ORDERING): Delete.
            * target.def (TARGET_RELAXED_ORDERING): Likewise.
            * config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Likewise.
            * config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Likewise.
            * config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Likewise.
            * config/sparc/linux.h (SPARC_RELAXED_ORDERING): Likewise.
            * config/sparc/linux64.h (SPARC_RELAXED_ORDERING): Likewise.
            * config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Likewise.
            * config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Likewise.
            * system.h (TARGET_RELAXED_ORDERING): Poison.

2015-06-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

            PR c++/66192
            PR target/66200
            * cp-tree.h (get_guard_cond): Adjust declaration
            * decl.c (expand_static_init): Use atomic load acquire
            and adjust call to get_guard_cond.
            * decl2.c (build_atomic_load_byte): New function.
            (get_guard_cond): Handle thread_safety.
            (one_static_initialization_or_destruction): Adjust call to
            get_guard_cond.

Modified:
    branches/google/gcc-4_9/gcc/config/alpha/alpha.c
    branches/google/gcc-4_9/gcc/config/ia64/ia64.c
    branches/google/gcc-4_9/gcc/config/rs6000/rs6000.c
    branches/google/gcc-4_9/gcc/config/sparc/linux.h
    branches/google/gcc-4_9/gcc/config/sparc/linux64.h
    branches/google/gcc-4_9/gcc/config/sparc/sparc.c
    branches/google/gcc-4_9/gcc/config/sparc/sparc.h
    branches/google/gcc-4_9/gcc/cp/cp-tree.h
    branches/google/gcc-4_9/gcc/cp/decl.c
    branches/google/gcc-4_9/gcc/cp/decl2.c
    branches/google/gcc-4_9/gcc/doc/tm.texi
    branches/google/gcc-4_9/gcc/doc/tm.texi.in
    branches/google/gcc-4_9/gcc/system.h
    branches/google/gcc-4_9/gcc/target.def

[Bug target/66200] GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[ramana at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

--- Comment #5 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
Author: ramana
Date: Wed Jun 10 07:43:31 2015
New Revision: 224313

URL: https://gcc.gnu.org/viewcvs?rev=224313&root=gcc&view=rev
Log:
Handle aarch64_guard1.C test

Sorry about missing this hunk in the original submission, was in my tree but I
hadn't spotted this as I was playing between the original AArch64
TARGET_RELAXED_ORDER and this patch.

Applied as obvious.

2015-06-09  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/66200
        PR target/66428
        PR c++/66192
        * g++.dg/abi/aarch64_guard1.C: Adjust test.


Modified:
    trunk/gcc/testsuite/ChangeLog
    trunk/gcc/testsuite/g++.dg/abi/aarch64_guard1.C

[Bug target/66200] GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[ramana at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

--- Comment #6 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
Author: ramana
Date: Fri Jun 12 09:49:41 2015
New Revision: 224411

URL: https://gcc.gnu.org/viewcvs?rev=224411&root=gcc&view=rev
Log:
Use atomics in guard.cc.

This provides proper definitions for _GLIBCXX_READ_MEM_BARRIER and
_GLIBCXX_WRITE_MEM_BARRIER, rewrites the guards in terms of proper
atomic extensions and removes internal uses of
_GLIBCXX_READ_MEM_BARRIER and _GLIBCXX_WRITE_MEM_BARRIER and replaces
them with equivalent atomics.

2015-06-12  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/66200
        PR c++/66192
        * * config/cpu/generic/atomic_word.h (_GLIBCXX_READ_MEM_BARRIER):
Define
        (_GLIBCXX_WRITE_MEM_BARRIER): Likewise
        * include/bits/shared_ptr_base.h: Use ACQ_REL barrier.
        * include/ext/atomicity.h: Likewise.
        * include/tr1/shared_ptr.h: Likewise.
        * libsupc++/guard.cc (__test_and_acquire): Rewrite with atomics.
        Update comment.
        (__set_and_release): Likewise.
        * testsuite/20_util/shared_ptr/cons/43820_neg.cc (test01): Adjust for
        line numbers.
        * testsuite/20_util/shared_ptr/cons/void_neg.cc: Likewise.
        * testsuite/tr1/2_general_utilities/shared_ptr/cons/43820_neg.cc:
        Likewise.

Modified:
    trunk/libstdc++-v3/ChangeLog
    trunk/libstdc++-v3/config/cpu/generic/atomic_word.h
    trunk/libstdc++-v3/include/bits/shared_ptr_base.h
    trunk/libstdc++-v3/include/ext/atomicity.h
    trunk/libstdc++-v3/include/tr1/shared_ptr.h
    trunk/libstdc++-v3/libsupc++/guard.cc
    trunk/libstdc++-v3/testsuite/20_util/shared_ptr/cons/43820_neg.cc
    trunk/libstdc++-v3/testsuite/20_util/shared_ptr/cons/void_neg.cc
   
trunk/libstdc++-v3/testsuite/tr1/2_general_utilities/shared_ptr/cons/43820_neg.cc

[Bug target/66200] GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[ramana at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

--- Comment #7 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
Author: ramana
Date: Tue Jun 16 15:26:41 2015
New Revision: 224524

URL: https://gcc.gnu.org/viewcvs?rev=224524&root=gcc&view=rev
Log:
Fix PR target/66200 on the 4.9 branch

Define TARGET_RELAXED_ORDERING and appropriate macros
for barriers.


2015-06-16  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/66200
        * config/aarch64/aarch64.c (TARGET_RELAXED_ORDERING): Define.

2015-06-16  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/66200
        * g++.dg/abi/aarch64_guard1.C: Adjust.

2015-06-16  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/66200
        * configure.host (host_cpu): Add aarch64 case.
        * config/cpu/aarch64/atomic_word.h: New file.


Added:
    branches/gcc-4_9-branch/libstdc++-v3/config/cpu/aarch64/
    branches/gcc-4_9-branch/libstdc++-v3/config/cpu/aarch64/atomic_word.h
Modified:
    branches/gcc-4_9-branch/gcc/ChangeLog
    branches/gcc-4_9-branch/gcc/config/aarch64/aarch64.c
    branches/gcc-4_9-branch/gcc/testsuite/ChangeLog
    branches/gcc-4_9-branch/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
    branches/gcc-4_9-branch/libstdc++-v3/ChangeLog
    branches/gcc-4_9-branch/libstdc++-v3/configure.host

[Bug target/66200] GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING

[ramana at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

--- Comment #8 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
Author: ramana
Date: Wed Jun 24 09:59:28 2015
New Revision: 224890

URL: https://gcc.gnu.org/viewcvs?rev=224890&root=gcc&view=rev
Log:
Fix PR target/66200

This applies the same fix for PR target/66200 for AArch64 on the GCC 5 branch
as on the 4.9 branch. On trunk we've fixed this differently by optimizing
the access to the guard variable using a load acquire style instruction.

2015-06-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/66200
        * g++.dg/abi/aarch64_guard1.C: Adjust.

2015-06-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/66200
        * configure.host (host_cpu): Add aarch64 case.
        * config/cpu/aarch64/atomic_word.h: New file.



Added:
    branches/gcc-5-branch/libstdc++-v3/config/cpu/aarch64/
    branches/gcc-5-branch/libstdc++-v3/config/cpu/aarch64/atomic_word.h
Modified:
    branches/gcc-5-branch/gcc/config/aarch64/aarch64.c
    branches/gcc-5-branch/gcc/testsuite/ChangeLog
    branches/gcc-5-branch/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
    branches/gcc-5-branch/libstdc++-v3/ChangeLog
    branches/gcc-5-branch/libstdc++-v3/configure.host