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Subject: [Bug target/66200] GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING
Date: Fri, 12 Jun 2015 09:50:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66200

--- Comment #6 from Ramana Radhakrishnan <ramana at gcc dot gnu.org> ---
Author: ramana
Date: Fri Jun 12 09:49:41 2015
New Revision: 224411

URL: https://gcc.gnu.org/viewcvs?rev=224411&root=gcc&view=rev
Log:
Use atomics in guard.cc.

This provides proper definitions for _GLIBCXX_READ_MEM_BARRIER and
_GLIBCXX_WRITE_MEM_BARRIER, rewrites the guards in terms of proper
atomic extensions and removes internal uses of
_GLIBCXX_READ_MEM_BARRIER and _GLIBCXX_WRITE_MEM_BARRIER and replaces
them with equivalent atomics.

2015-06-12  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/66200
        PR c++/66192
        * * config/cpu/generic/atomic_word.h (_GLIBCXX_READ_MEM_BARRIER):
Define
        (_GLIBCXX_WRITE_MEM_BARRIER): Likewise
        * include/bits/shared_ptr_base.h: Use ACQ_REL barrier.
        * include/ext/atomicity.h: Likewise.
        * include/tr1/shared_ptr.h: Likewise.
        * libsupc++/guard.cc (__test_and_acquire): Rewrite with atomics.
        Update comment.
        (__set_and_release): Likewise.
        * testsuite/20_util/shared_ptr/cons/43820_neg.cc (test01): Adjust for
        line numbers.
        * testsuite/20_util/shared_ptr/cons/void_neg.cc: Likewise.
        * testsuite/tr1/2_general_utilities/shared_ptr/cons/43820_neg.cc:
        Likewise.

Modified:
    trunk/libstdc++-v3/ChangeLog
    trunk/libstdc++-v3/config/cpu/generic/atomic_word.h
    trunk/libstdc++-v3/include/bits/shared_ptr_base.h
    trunk/libstdc++-v3/include/ext/atomicity.h
    trunk/libstdc++-v3/include/tr1/shared_ptr.h
    trunk/libstdc++-v3/libsupc++/guard.cc
    trunk/libstdc++-v3/testsuite/20_util/shared_ptr/cons/43820_neg.cc
    trunk/libstdc++-v3/testsuite/20_util/shared_ptr/cons/void_neg.cc
   
trunk/libstdc++-v3/testsuite/tr1/2_general_utilities/shared_ptr/cons/43820_neg.cc